US4538247A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Redundant rows in integrated circuit memories
Assignee: Fairchild Semiconductor Corp
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Filing: 1983-01-14
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Granted: 1985-08-27
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Expires: 2003-01-14
Abstract
Abstract Decoding apparatus for an integrated circuit memory having normal rows of memory cells 10 and at least one selectively connectable redundant second row of memory cells 31 for being connected in place of one of the first rows 10 includes a redundant decoder (transistors 32, 33. . . n) connected to each of the redundant rows 31, the redundant decoder including a plurality of selectable connections (F 1 , F 2 . . . F n ) for creating an address for each of the at least one redundant rows 31; a control signal generating circuit (gates 45, 46, and 47) for generating a control signal of a first state until an address is supplied to the memory and of a second state if any of the redundant rows 31 are selected by the address, and another decoder (transistors 23 and 39) connected to receive control signal φ C from the generating circuit for controlling normal rows 10 and the redundant row 31 in response thereto.
Inventors
- 👤 Kalyanasundaram Venkateswaran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:48
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/781
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
184 words
Decoding apparatus for an integrated circuit memory having first rows of memory cells, each first row being selectable by a row address, including at least one address bit, and having at least one second row selectively connectable in place of one of the first rows, the apparatus comprising: at least one redundant decoder means, each redundant decoder means being connected to a second row, including a plurality of selectable connections for creating an address for the connected second row, and including means for producing an address signal of a first level if the row address corresponds to the created address and of a second level if the row address does not correspond to the created address; logic means for generating a control signal of a first state until an address bit is supplied to the memory and of a second state if at least one address signal from the at least one second row is of the first level; and decoder means connected to each first row to receive the control signal from the logic means for controlling the first rows in response thereto.
Claim 2
Dependent Claim
184 words
Decoding apparatus for an integrated circuit memory having first rows of memory cells, each first row being selectable by a row address, including at least one address bit, and having at least one second row selectively connectable in place of one of the first rows, the apparatus comprising: at least one redundant decoder means, each redundant decoder means being connected to a second row, including a plurality of selectable connections for creating an address for the connected second row, and including means for producing an address signal of a first level if the row address corresponds to the created address and of a second level if the row address does not correspond to the created address; logic means for generating a control signal of a first state until an address bit is supplied to the memory and of a second state if at least one address signal from the at least one second row is of the first level; and decoder means connected to each first row to receive the control signal from the logic means for controlling the first rows in response thereto.
Claim 3
Dependent Claim
37 words
The apparatus of claim 1 wherein the logic means comprises: first means connected to receive the address signal from each of the at least one second row; and second means connected to receive a selected address bit.
Claim 4
Dependent Claim
32 words
The apparatus of claim 2 wherein the first means supplies a first output signal if any of the address signals for the at least one second row is of the first level.
Claim 5
Dependent Claim
13 words
The apparatus of claim 3 wherein the first means comprises an OR gate.
Claim 6
Dependent Claim
25 words
The apparatus of claim 3 wherein the second means is connected to receive a complement of the address bit and supply a second output signal.
Claim 7
Dependent Claim
14 words
The apparatus of claim 5 wherein the second means comprises an exclusive OR gate.
Claim 8
Dependent Claim
22 words
The apparatus of claim 6 wherein both of the first and second output signals are connected as inputs to a logic gate.
Claim 9
Dependent Claim
13 words
The apparatus of claim 7 wherein the logic gate comprises a NAND gate.
Claim 10
Dependent Claim
14 words
The apparatus of claim 7 wherein the logic gate output is the control signal.
Claim 11
Dependent Claim
21 words
The apparatus of claim 1 wherein each redundant decoder comprises a plurality of transistors each adapted to receive an address bit.
Claim 12
Dependent Claim
26 words
The apparatus of claim 10 wherein each transistor is connected to the second row and a fusing means is serially connected between each transistor and ground.
Claim 13
Dependent Claim
15 words
The apparatus of claim 11 wherein each fusing means comprises a laser destructible electrical connection.
Claim 14
Dependent Claim
18 words
The apparatus of claim 11 wherein each transistor includes a control electrode connected to receive an address bit.
Claim 15
Dependent Claim
11 words
The apparatus of claim 1 having at least two second rows.
Claim 16
Dependent Claim
11 words
The apparatus of claim 3 having at least two second rows.
Claim 17
Dependent Claim
11 words
The apparatus of claim 6 having at least two second rows.
Claim 18
Dependent Claim
11 words
The apparatus of claim 9 having at least two second rows.
Claim 19
Dependent Claim
11 words
The apparatus of claim 13 having at least two second rows.
References Cited (Backward Citations)
US4250570A
Cited
US4250570B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-26 | 1989-02-25 | 1989-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-26 | 1993-02-25 | 1993-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-26 | 1997-02-25 | 1997-08-27 | $7700.00 | Window Closed / Lapsed |