US5375090A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Sharp Corp
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Filing: 1993-01-08
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Granted: 1994-12-20
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Expires: 2013-01-08
Abstract
Abstract A semiconductor memory device of the present invention includes a plurality of blocks. Each of the blocks includes: a memory cell group including redundancy cells; a memory cell group selection decoder for, in response to an address signal indicative of an address in the memory cell group, selecting a memory cell having the address; and a redundancy decoder in which any address included in a memory cell group in any one of the blocks except for the block to which the redundancy decoder belongs can be registered, the redundancy decoder outputting a prescribed signal to all of the memory cell group selection decoders in the respective blocks, when the address indicated by the address signal is identical with the registered address. Each the memory cell group selection decoding comprising: forcedly selecting means for, when the prescribed signal is supplied from the redundancy decoder in the block to which the memory cell group selection decoder belongs, forcedly selecting the memory cell group in the block; and forcedly non-selecting means for, when the prescribed signal is supplied from the redundancy decoder in one of the blocks except for the block to which the memory cell group selection decoder belongs, forcedly not selecting the memory cell group in the block to which the memory cell group selection decoder belongs.
Inventors
- 👤 Makoto Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:16
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
202 words
A semiconductor memory device comprising a plurality of blocks, each of said blocks comprising: a memory cell group including redundancy cells; a memory cell group selection decoder for, in response to an address signal indicative of an address in said memory cell group, selecting a memory cell having said address; and a redundancy decoder in which any address included in the memory cell group in any one of said blocks can be registered, said redundancy decoder outputting a prescribed signal to all of said memory cell group selection decoders in said respective blocks, when the address indicated by said address signal is identical with the registered address, each of said memory cell group selection decoders comprising: forcedly selecting means for, when said prescribed signal is supplied from the redundancy decoder in the same respective block as said memory cell group selection decoder, forcedly selecting the memory cell group in said same block; and forcedly non-selecting means for, when said prescribed signal is supplied from the redundancy decoder in one of said other respective blocks to the redundancy decoder in said same block, forcedly not selecting the memory cell group in said same block to which said memory cell group selection decoder belongs.
Claim 2
Dependent Claim
202 words
A semiconductor memory device comprising a plurality of blocks, each of said blocks comprising: a memory cell group including redundancy cells; a memory cell group selection decoder for, in response to an address signal indicative of an address in said memory cell group, selecting a memory cell having said address; and a redundancy decoder in which any address included in the memory cell group in any one of said blocks can be registered, said redundancy decoder outputting a prescribed signal to all of said memory cell group selection decoders in said respective blocks, when the address indicated by said address signal is identical with the registered address, each of said memory cell group selection decoders comprising: forcedly selecting means for, when said prescribed signal is supplied from the redundancy decoder in the same respective block as said memory cell group selection decoder, forcedly selecting the memory cell group in said same block; and forcedly non-selecting means for, when said prescribed signal is supplied from the redundancy decoder in one of said other respective blocks to the redundancy decoder in said same block, forcedly not selecting the memory cell group in said same block to which said memory cell group selection decoder belongs.
Claim 3
Dependent Claim
47 words
A semiconductor memory device according to claim 1, wherein a selected one of said redundancy decoders has registered therein addresses of failure memory cells included in the same block as said selected redundancy decoder and addresses of failure memory cells at least one of said other blocks.
Claim 4
Dependent Claim
79 words
A semiconductor memory device according to claim 1, wherein each or said memory cell group selection decoders selects the memory cell group in the block to which said respective memory cell group selection decoder belongs when said address signal indicates the address in said memory cell group in the same block to which said respective memory cell group selection decoder belongs, and said respective memory cell group selection decoder receives none of said prescribed signals from said redundancy decoders.
Claim 5
Dependent Claim
49 words
A semiconductor memory device according to claim 3, wherein, when said respective memory cell group selection decoder selects the memory cell group included in the same block as said respective memory cell group selection decoder, a memory cell corresponding to the address indicated by said address signal is accessed.
Claim 6
Dependent Claim
58 words
A semiconductor memory device according to claim 1, wherein when said memory cell group selection decoders select the memory cell group in the block to which said respective memory cell group selection decoder belongs by said forcedly selecting means, a redundancy cell corresponding to the address indicated by said address signal in said memory cell group is accessed.
Claim 7
Dependent Claim
205 words
A semiconductor memory method in a semiconductor memory device comprising a plurality of blocks, each of said blocks comprising: a memory cell group including redundancy cells; a memory cell group selection decoder for, in response to an address signal indicative of an address in said memory cell group, selecting a memory cell having said address; and a redundancy decoder in which any address included in the memory cell group in any one of said blocks can be registered, said redundancy decoder outputting a prescribed signal to all of said memory cell group selection decoders in said respective blocks, when the address indicated by said address signal is identical with the registered address, said method comprising in each of said memory cell group selection decoders the steps of: forcedly selecting, when said prescribed signal is supplied from the redundancy decoder in the same respective block as said memory cell group selection decoder, the memory cell group in said same block; and forcedly not selecting, when said prescribed signal is supplied from the redundancy decoder in one of said other respective blocks to the redundancy decoder in said same block, the memory cell group in said same block to which said memory cell group selection decoder belongs.
Claim 8
Dependent Claim
205 words
A semiconductor memory method in a semiconductor memory device comprising a plurality of blocks, each of said blocks comprising: a memory cell group including redundancy cells; a memory cell group selection decoder for, in response to an address signal indicative of an address in said memory cell group, selecting a memory cell having said address; and a redundancy decoder in which any address included in the memory cell group in any one of said blocks can be registered, said redundancy decoder outputting a prescribed signal to all of said memory cell group selection decoders in said respective blocks, when the address indicated by said address signal is identical with the registered address, said method comprising in each of said memory cell group selection decoders the steps of: forcedly selecting, when said prescribed signal is supplied from the redundancy decoder in the same respective block as said memory cell group selection decoder, the memory cell group in said same block; and forcedly not selecting, when said prescribed signal is supplied from the redundancy decoder in one of said other respective blocks to the redundancy decoder in said same block, the memory cell group in said same block to which said memory cell group selection decoder belongs.
Claim 9
Dependent Claim
49 words
A semiconductor memory method according to claim 6, comprising a step of registering in a selected one of said redundancy decoders addresses of failure memory cells in the same block as said selected redundancy decoder and addresses of failure memory cells in at least one of said other blocks.
Claim 10
Dependent Claim
86 words
A semiconductor memory method according to claim 6, comprising a step of selecting the memory cell group in the block to which a selected one of said memory cell group selection decoders belongs by means of said selected memory cell group selection decoder when said address signal indicates the address in said memory cell group in said block to which said selected memory cell group selection decoder belongs, and said selected memory cell group selection decoder receives none of said prescribed signals from said redundancy decoders.
Claim 11
Dependent Claim
52 words
A semiconductor memory method according to claim 8, comprising a step of accessing a memory cell corresponding to the address indicated by said address signal when said selected memory cell group selection decoder selects the memory cell group which belongs to the same block as said selected memory cell group selection decoder.
Claim 12
Dependent Claim
60 words
A semiconductor memory method according to claim 6, comprising a step of accessing, when said memory cell group selection decoders select the memory cell group in the block to which said respective memory cell group selection decoder belongs by said forcedly selecting step, a redundancy cell corresponding to the address indicated by said address signal in said memory cell group.
References Cited (Backward Citations)
US4837747A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-19 | 1998-06-20 | 1998-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-19 | 2002-06-20 | 2002-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-19 | 2006-06-20 | 2006-12-20 | $7700.00 | Window Closed / Lapsed |