CMOS thin-film transistor having split gate structure

Claim 1

A thin film semiconductor device for use as an inverter having an input terminal and an output terminal such that when a zero or relatively low voltage signal is input at said input terminal, a relatively high voltage signal is generated at the output terminal of said inverter, comprising: a substrate; a first semiconductor layer and a second semiconductor layer formed on said substrate; an N-type thin film transistor including a first channel region formed in said first semiconductor layer, a first source region formed in said first semiconductor layer, a first drain region formed in said first semiconductor layer, a first gate insulating film formed on said first channel region, and a first gate electrode formed on said first gate insulating film; a P-type thin film transistor including a second channel region formed in said second semiconductor layer, a second source region formed in said second semiconductor layer, a second drain region formed in said second semiconductor layer, a second gate insulating film formed on said second channel region, and a second gate electrode formed on said second gate insulating film, wherein said input terminal is connected to said first and second gate electrodes and said output terminal is connected to said first and second drain regions, said first gate electrode having a plurality of first gate electrode sections spaced apart along a channel length direction extending between the first source and drain regions, wherein when a substantially zero voltage is applied to said input terminal, leakage current between said first drain region and said first source region is minimized; wherein a length of the first channel region is dimensioned to balance resistance characteristics of the thin film semiconductor device; and wherein N-type regions are formed in portions of the first channel region not covered by the gate electrode sections so as to form a plurality of channel subregions spaced apart along said channel length direction, each of the channel subregions being adjacent to the respective first gate electrode sections, whereby p-n junctions are formed across the first channel region when a relatively high voltage is applied between the first source region and the first drain region of the N-type thin film transistor.