Abstract A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.
A one-chip memory device comprising: a dynamic RAM an operation of which is controlled by a row address strobe signal, a column address strobe signal and a write enable signal; and a control circuit which responds to at least a low level of said write enable signal at a time of a falling edge of said row address strobe signal, wherein said operation of said dynamic RAM is set to a specific mode by an output of said control circuit in response to said low level of said write enable signal at said time of said falling edge of said row address strobe signal.
Claim 2
Dependent Claim
104 words
A one-chip memory device comprising: a dynamic RAM an operation of which is controlled by a row address strobe signal, a column address strobe signal and a write enable signal; and a control circuit which responds to at least a low level of said write enable signal at a time of a falling edge of said row address strobe signal, wherein said operation of said dynamic RAM is set to a specific mode by an output of said control circuit in response to said low level of said write enable signal at said time of said falling edge of said row address strobe signal.
Claim 3
Dependent Claim
25 words
A one-chip memory device according to claim 1, wherein a write operation to said dynamic RAM is carried out in accordance with said specific mode.
Claim 4
Dependent Claim
48 words
A one-chip memory device according to claim 1, wherein said operation of said dynamic RAM is set to said specific mode by an output of a register which stores mode designation signals supplied from external address terminals, and which is controlled by said output of said control circuit.
Claim 5
Dependent Claim
48 words
A one-chip memory device according to claim 2, wherein said operation of said dynamic RAM is set to said specific mode by an output of a register which stores mode designation signals supplied from external address terminals, and which is controlled by said output of said control circuit.