US4095268A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for stopping and restarting the operation of a data processor
Assignee: Hitachi Ltd
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Filing: 1976-08-09
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Granted: 1978-06-13
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Expires: 1996-08-09
Abstract
Abstract In an electronic computer system wherein, when a microprogram-controlled central processing unit receives a stop signal from a console, the contents of a group of registers are assigned to predetermined fixed areas in a main memory and, in response to a start signal, the assigned contents of the group of registers are delivered from the fixed areas to the group of registers. The reading and writing of the contents of the group of registers within the central processing unit is effected for the fixed areas of the main memory in which the contents are assigned.
Inventors
- 👤 Yoshiki Kobayashi
- 👤 Tadaaki Bandoh
- 👤 Hideo Maejima
- 👤 Hajime Yasuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 07:46
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/461
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
154 words
A system for stopping and restarting the operation of a data processor, which has a central processing unit which is operative under the existence of a timing signal, a console from which start and stop signals are supplied to the central processing unit, and a main memory, the contents of which can be directly accessed by the central processing unit and the console, the system comprising means for suspending an executed program and assigning the contents of a group of registers within said central processing unit to predetermined fixed areas of said main memory in response to a stop signal from said console, means for stopping the timing signal of said central processing unit after said assignment of the contents, and means for restarting the timing signal of said central processing unit and restoring the contents of said fixed areas to said group of registers in response to the start signal from said console.
Claim 2
Independent Claim
154 words
A system for stopping and restarting the operation of a data processor, which has a central processing unit which is operative under the existence of a timing signal, a console from which start and stop signals are supplied to the central processing unit, and a main memory, the contents of which can be directly accessed by the central processing unit and the console, the system comprising means for suspending an executed program and assigning the contents of a group of registers within said central processing unit to predetermined fixed areas of said main memory in response to a stop signal from said console, means for stopping the timing signal of said central processing unit after said assignment of the contents, and means for restarting the timing signal of said central processing unit and restoring the contents of said fixed areas to said group of registers in response to the start signal from said console.
Claim 3
Dependent Claim
51 words
A system according to claim 1, further including means for, during the stop state of the timing signal, carrying out read/write operations, normally assigned for the contents of said registers, on the contents of said predetermined fixed areas of said main memory, in response to read/write control signals from said console.
Claim 4
Dependent Claim
80 words
A system according to claim 1, wherein said console is provided with address switches and an address rotary switch designating the upper digits and lower digits of addresses of said main memory by said address switches and said address rotary switch, respectively, and including control means for causing the fixed areas of said main memory to correspond with the lower digits of said addresses so as to designate said fixed areas of said main memory by said address rotary switch.
Claim 5
Dependent Claim
162 words
In a system for stopping and restarting the operation of a data processor, which has a central processing unit which is operative under the existence of a timing signal, a console from which start and stop signals are supplied to the central processing unit and a main memory, the contents of which can be directly accessed by the central processing unit and the console, a method of operating said system comprising the steps of: (a) temporarily storing the contents of registers within said central processing unit in predetermined fixed areas of said main memory in response to a stop signal from said console and stopping the timing signal of said central processing unit after said assignment of the contents of said registers; and (b) upon receipt of a start signal from said console, restarting the timing signal of said central processing unit and restoring the contents of said fixed areas of said main memory to said registers within said central processing unit.
Claim 6
Dependent Claim
162 words
In a system for stopping and restarting the operation of a data processor, which has a central processing unit which is operative under the existence of a timing signal, a console from which start and stop signals are supplied to the central processing unit and a main memory, the contents of which can be directly accessed by the central processing unit and the console, a method of operating said system comprising the steps of: (a) temporarily storing the contents of registers within said central processing unit in predetermined fixed areas of said main memory in response to a stop signal from said console and stopping the timing signal of said central processing unit after said assignment of the contents of said registers; and (b) upon receipt of a start signal from said console, restarting the timing signal of said central processing unit and restoring the contents of said fixed areas of said main memory to said registers within said central processing unit.
Claim 7
Dependent Claim
53 words
A method according to claim 4, further including the step of: (c) during the stop state of the timing signal, carrying out read/write operations, normally assigned for the contents of said registers, on the contents of said predetermined fixed areas of said main memory, in response to read/write control signals from said console.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-12 | 1981-12-12 | 1982-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-12 | 1985-12-12 | 1986-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-12 | 1989-12-12 | 1990-06-13 | $7700.00 | Window Closed / Lapsed |