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US3974480A Expired / Lapsed US ⏱️ 0.0 years remaining

Data processing system, specially for real-time applications

Assignee: Individual
•
Filing: 1974-05-08
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Granted: 1976-08-10
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Expires: 1994-05-08
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Abstract

Abstract This invention relates to a data processing system, specially for real-time applications. This system comprises a processor having a relatively small number of registers, and safeguard storages consisting each of a stack of sequentially addressable registers. When a program being performed is interrupted, all the information contents of the processor registers are transferred to at least one safeguard storage. The transferred information are subsequently extracted, upon resumption of the interrupted program, from the safeguard storage, in a sequential order reverse with respect to the order in which they had been previously transferred. This system is specially adapted for controlling industrial processes.

Inventors

  • 👤 Francois Gernelle

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 07:31
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/461

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 223 words
Data processing system, particularly for real-time applications requiring a relatively moderate processing capability, which comprises: a. a processor comprising: i. a plurality of registers, j. means for interrupting a processing program or subprogram, k. means for performing said processing program or subprogram, and for performing at least one subprogram necessary for a real-time application upon the occurrence of an interruption caused by said interrupting means, and subsequently, upon completion of said subprogram necessary for a real-time application, for resuming the performance of the previously interrupted program or subprogram, b. a plurality of safeguard storages consisting each of a stack of N independent and sequentially addressable registers, c. means for controlling a transfer of the contents of all the registers of said processor to at least one of said safeguard storages in a predetermined sequential order when a program or subprogram is interrupted and for re-loading the registers of said processor with said contents previously transferred to at least one of said safeguard storages in a sequential order reverse with respect to said predetermined order when resuming said interrupted program or subprogram, d. and at least one bus line connecting said registers of said processor to said safeguard storages for transferring said contents, and said interrupting means to said performing means for transmitting an interrupt signal from said interrupting means to said performing means.
Claim 2
Dependent Claim 223 words
Data processing system, particularly for real-time applications requiring a relatively moderate processing capability, which comprises: a. a processor comprising: i. a plurality of registers, j. means for interrupting a processing program or subprogram, k. means for performing said processing program or subprogram, and for performing at least one subprogram necessary for a real-time application upon the occurrence of an interruption caused by said interrupting means, and subsequently, upon completion of said subprogram necessary for a real-time application, for resuming the performance of the previously interrupted program or subprogram, b. a plurality of safeguard storages consisting each of a stack of N independent and sequentially addressable registers, c. means for controlling a transfer of the contents of all the registers of said processor to at least one of said safeguard storages in a predetermined sequential order when a program or subprogram is interrupted and for re-loading the registers of said processor with said contents previously transferred to at least one of said safeguard storages in a sequential order reverse with respect to said predetermined order when resuming said interrupted program or subprogram, d. and at least one bus line connecting said registers of said processor to said safeguard storages for transferring said contents, and said interrupting means to said performing means for transmitting an interrupt signal from said interrupting means to said performing means.
Claim 3
Dependent Claim 88 words
Data processing system as set forth in claim 1, further comprising a plurality of rapid peripheral units connected to the same said bus line, and channels connected to said rapid peripheral units and to said processor through said bus line for exchanging information between said processor and said rapid peripheral units, at least some of said safeguard storages being inserted in said information exchange channels and connected to said processor through said bus line and to said rapid peripheral units for operation as buffer storages under time-sharing conditions.
Claim 4
Dependent Claim 56 words
Data processing system as set forth in claim 1, further comprising safeguard storages connected to said processor through said bus line for temporarily storing, in at least some of these safeguard storages, immediate results and subprogram parameters in said predetermined sequential order and between two selected steps of said program or of one of said subprograms.
Claim 5
Dependent Claim 43 words
Data processing system as set forth in claim 1, further comprising read-only storages connected to said bus line for recording the instructions of said program and subprograms, and live storages connected to said bus line for recording parameters of said program and subprograms.
Claim 6
Dependent Claim 58 words
Data processing system as set forth in claim 1, further comprising slow peripheral units having arbitrary numbers of inputs and outputs, and standardized couplers having all same predetermined numbers of inputs and outputs, each of said coupler inputs and outputs being adapted to be used for coupling any one of said slow peripheral units to said bus line.
Claim 7
Dependent Claim 47 words
Data processing system as set forth in claim 1, wherein said bus line comprises a plurality of conductors and a plurality of identical connectors for connecting storages and peripheral units to said bus line, each conductor of said bus line extending to each one of said connectors.

References Cited (Backward Citations)

US3286239A Cited
US3568158A Cited
US3699532A Cited
US3639911A Cited
US3757307A Cited
US3725868A Cited
US3688263A Cited
US3805038A Cited
US3838260A Cited
US3838261A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-08-10 1980-02-09 1980-08-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-08-10 1984-02-09 1984-08-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-08-10 1988-02-09 1988-08-10 $7700.00 Window Closed / Lapsed

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