US3838261A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interrupt control circuit for central processor of digital communication system
Assignee: AG Communication Systems Corp
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Filing: 1973-09-14
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Granted: 1974-09-24
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Expires: 1993-09-14
Abstract
Abstract The control and maintenance complex of a TSPS telephone system is provided with duplicate copies of a programmable central data processor, instruction storage, process storage and peripheral units which interface with the telephone network. When a fault is detected, the system enters a recovery phase to try to obtain a fault-free combination. Recovery programs have priority over call processing programs. An interrupt control circuit (ICC) is present in each central processor; and the ICC in the active central processor, upon fault detection by the central processor, controls the execution of maintenance interrupts. The ICC establishes priority of recovery programs, inhibits the call for recovery programs of lesser priority than the one being executed, and generates an Interrupt Control Circuit Sequence Level signal which performs many functions in the other circuits of the central processor, including those necessary to call and run a recovery program without losing data when the interrupt occurs.
Inventors
- 👤 V Rice
- 👤 J Mele
- 👤 R Buhrke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:54
CPC Classifications
G; G06; G06F; G06F11/00; H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/54; H04Q3/545; H04Q3/54541; H04Q3/54558
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
383 words
In a data processing system having first and second central data processors, instruction stores, process stores, and peripheral controllers, each said processors including processing circuits and maintenance circuits and further including general programs, a system recovery program, and a plurality of subsystem recovery programs, said recovery programs being stored in known locations in memory and each including an associated first recovery program instruction storage location, said system being adapted wherein only one of said processors is active at one time and the other is standby, each of said processors being further provided with recovery control circuit means for generating system error level signals, malfunction monitor circuit means for generating subsystem error level signals, each representative of malfunctions in selected subsystems of said system, the improvement comprising: interrupt control circuit means in each of said central processors responsive to said system error level signals and to said subsystem error level signals and to programmed error level signals for interrupting a program being executed and for switching to a recovery program in predetermined order of priority and including: a plurality of interrupt bistable circuit means, each actuated by an associated error level signal to generate an error level signal representative of the recovery program associated therewith; priority circuit means responsive to said error level signals of said interrupt bistable circuit means for generating an interrupt control circuit sequence level to initiate a recovery cycle, and for generating priority level signaLs representative of the order of priority of each of said error level signals; a plurality of inhibit circuit means, one associated with each of said interrupt bistable circuit means of priority less than the highest and responsive to said priority level signals for inhibiting actuation of its associated interrupt bistable circuit means when a recovery program is being run of a higher priority; input/output circuit means interfacing said central processor with said instruction stores, process stores, and peripheral controllers, and including a first instruction store inhibit bistable circuit associated with one of said instruction stores and a second instruction store inhibit bistable circuit associated with said second instruction store: and further comprising means for communicating said interrupt control circuit sequence level to reset said first and second instruction store inhibit bistable circuits, thereby enabling said system to freely manipulate central processor and instruction store combinations.
Claim 2
Dependent Claim
383 words
In a data processing system having first and second central data processors, instruction stores, process stores, and peripheral controllers, each said processors including processing circuits and maintenance circuits and further including general programs, a system recovery program, and a plurality of subsystem recovery programs, said recovery programs being stored in known locations in memory and each including an associated first recovery program instruction storage location, said system being adapted wherein only one of said processors is active at one time and the other is standby, each of said processors being further provided with recovery control circuit means for generating system error level signals, malfunction monitor circuit means for generating subsystem error level signals, each representative of malfunctions in selected subsystems of said system, the improvement comprising: interrupt control circuit means in each of said central processors responsive to said system error level signals and to said subsystem error level signals and to programmed error level signals for interrupting a program being executed and for switching to a recovery program in predetermined order of priority and including: a plurality of interrupt bistable circuit means, each actuated by an associated error level signal to generate an error level signal representative of the recovery program associated therewith; priority circuit means responsive to said error level signals of said interrupt bistable circuit means for generating an interrupt control circuit sequence level to initiate a recovery cycle, and for generating priority level signaLs representative of the order of priority of each of said error level signals; a plurality of inhibit circuit means, one associated with each of said interrupt bistable circuit means of priority less than the highest and responsive to said priority level signals for inhibiting actuation of its associated interrupt bistable circuit means when a recovery program is being run of a higher priority; input/output circuit means interfacing said central processor with said instruction stores, process stores, and peripheral controllers, and including a first instruction store inhibit bistable circuit associated with one of said instruction stores and a second instruction store inhibit bistable circuit associated with said second instruction store: and further comprising means for communicating said interrupt control circuit sequence level to reset said first and second instruction store inhibit bistable circuits, thereby enabling said system to freely manipulate central processor and instruction store combinations.
Claim 3
Dependent Claim
122 words
The system of claim 1 wherein said priority circuit means is responsive to the output signals of said interrupt bistable circuit means and to the output signals of said inhibit circuit means for generating a plurality of address signals representative of the state of said priority circuit means and of the recovery program of highest order being called for by the system; and wherein said system further comprises: interrupt address bus means for communicating said signals representative of the priority of the recovery program being called for to the processing circuits of said central processor for generating address signals representative of a memory location containing a transfer instruction, said transfer instruction providing access to the first instruction of the desired recovery program.
Claim 4
Dependent Claim
62 words
The system of claim 1 wherein each of said subsystem error level signals is representative respectively and in order of priority of a central processor error level signal, an instruction store error level signal, a processor store error level signal, and a peripheral unit error level signal, and wherein the highest priority error level signal is a system recovery error level signal.
Claim 5
Dependent Claim
56 words
The system of claim 3 further comprising circuit means responsive to said recovery control error level signal and to a manually generated error level signal and to a program controlled error level signal for actuating said first order priority interrupt bistable circuit means irrespective of the data processing or recovery program being run at the time.
Claim 6
Dependent Claim
43 words
The system of claim 1 further comprising malfunction monitor circuit means including match register circuit means; and circuit means for storing the failing address responsive to said interrupt control circuit sequence level signal in said match registers of said malfunction monitor circuit means.
Claim 7
Dependent Claim
28 words
The system of claim 5 further comprising recovery program timer means reset by said interrupt control circuit sequence level signal for timing the execution of said recovery programs.
Claim 8
Dependent Claim
44 words
The system of claim 1 further comprising maintenance access circuit means responsive to program control signals for selectively controlling the states of said inhibit circuit means, whereby said interrupt bistable circuit means may be controlled independently of said inhibit circuit means for diagnostic testing.
Claim 9
Dependent Claim
28 words
The system of claim 7 wherein said maintenance access circuit means further includes means for selectively resetting the states of said interrupt bistable circuit means under program control.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-23 | 1978-03-25 | 1978-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-23 | 1982-03-25 | 1982-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-23 | 1986-03-25 | 1986-09-24 | $7700.00 | Window Closed / Lapsed |