US5517626A — Open high speed bus for microcomputer system

Claim 1

Independent Claim 195 words

A local system bus for a micro-processor based computer system including a plurality of controllers connected between the local system bus and at least one micro-processor, a system memory or an I/O bus, one of the controllers being a bus master and another being a bus slave during a bus transaction, the local system bus comprising: lines for carrying an address driven by the bus master and received by the bus slave; lines for carrying data driven by the bus master and received by the bus slave during a write transaction or driven by the bus slave and received by the bus master during a read transaction; lines for carrying signals generated by the bus master and received by the bus slave, for defining a transaction in progress; lines for carrying control signals for micro-processor operations; lines for carrying status signals asserted by the bus slave for indicating a status of the bus slave further comprising lines for carrying interrupt signals; and lines for carrying arbitration signals, wherein the lines for carrying arbitration signals comprise a line for carrying a bus hold request for permitting another controller to gain control of the local system bus.

Claim 2

Dependent Claim 195 words

A local system bus for a micro-processor based computer system including a plurality of controllers connected between the local system bus and at least one micro-processor, a system memory or an I/O bus, one of the controllers being a bus master and another being a bus slave during a bus transaction, the local system bus comprising: lines for carrying an address driven by the bus master and received by the bus slave; lines for carrying data driven by the bus master and received by the bus slave during a write transaction or driven by the bus slave and received by the bus master during a read transaction; lines for carrying signals generated by the bus master and received by the bus slave, for defining a transaction in progress; lines for carrying control signals for micro-processor operations; lines for carrying status signals asserted by the bus slave for indicating a status of the bus slave further comprising lines for carrying interrupt signals; and lines for carrying arbitration signals, wherein the lines for carrying arbitration signals comprise a line for carrying a bus hold request for permitting another controller to gain control of the local system bus.

Claim 3

Dependent Claim 24 words

A local system bus as in claim 1, further comprising at least one line for carrying a signal for partial read and write operations.

Claim 4

Dependent Claim 24 words

A local system bus as in claim 1, further comprising at least one line for carrying a signal indicating a parity of the data.

Claim 5

Dependent Claim 32 words

A local system bus as in claim 1, wherein the lines for defining a transaction comprise a line for carrying a signal indicating whether the transaction involves memory operations or I/O operations.

Claim 6

Dependent Claim 29 words

A local system bus as in claim 1, wherein the lines for defining a transaction comprise a line for carrying a signal indicating data transactions or instruction fetch transactions.

Claim 7

Dependent Claim 32 words

A local system bus as in claim 1, wherein the lines for defining a transaction comprise a line for carrying a signal indicating whether the transaction involves write operations or read operations.

Claim 8

Dependent Claim 34 words

A local system bus as in claim 1, wherein the lines for defining a transaction comprise a line for carrying a signal indicating whether the transaction is a normal transaction or a locked transaction.

Claim 9

Dependent Claim 25 words

A local system bus as in claim 1, wherein the lines for defining a transaction comprise a line for carrying a signal supporting copy-back operations.

Claim 10

Dependent Claim 25 words

A local system bus as in claim 1, wherein the lines for defining a transaction comprise a line carrying a signal for write-through cache operations.

Claim 11

Dependent Claim 29 words

A local system bus as in claim 1, wherein the control signal lines comprise a line carrying a signal indicating a valid address being on the local system bus.

Claim 12

Dependent Claim 27 words

A local system bus as in claim 1, wherein the control signal lines comprise a line for carrying a signal indicating an end of a data cycle.

Claim 13

Dependent Claim 33 words

A local system bus as in claim 1, wherein the control signal lines comprise a line for carrying a signal indicating a bit size of a bus master involved in a current cycle.

Claim 14

Dependent Claim 33 words

A local system bus as in claim 1, wherein the control signal lines comprise a line for carrying a signal indicating a bit size of a bus slave recipient of a current cycle.

Claim 15

Dependent Claim 32 words

A local system bus as in claim 1, wherein the control signal lines comprise a line for carrying a signal indicating a bus slave being ready to receive a next line address.

Claim 16

Dependent Claim 44 words

A local system bus as in claim 1, wherein the lines for carrying status signals comprise a line for carrying a signal indicating the bus slave having provided valid data in response to a read or having accepted data in response to a write.

Claim 17

Dependent Claim 34 words

A local system bus as in claim 1, wherein the lines for carrying status signals comprise a line for carrying a signal indicating the bus slave being not ready to handle a required transaction.

Claim 18

Dependent Claim 36 words

A local system bus as in claim 1, wherein the lines for carrying status signals comprise a line for carrying a signal asserted by a bus slave for extending a snoop cycle of a current transaction.

Claim 19

Dependent Claim 36 words

A local system bus as in claim 1, wherein the lines for carrying status signals comprise a line for carrying a signal indicating a parity error on the lines for carrying data during a data cycle.

Claim 20

Dependent Claim 39 words

A local system bus as in claim 1, wherein the lines for carrying status signals comprise a line for carrying a signal indicating that a non-master cache controller will retain a copy of addressed data in a current transaction.

Claim 21

Dependent Claim 29 words

A local system bus as in claim 1, wherein the lines for carrying status signals comprise a line for carrying a signal indicating whether a current transaction is cacheable.

Claim 22

Dependent Claim 33 words

A local system bus as in claim 1, wherein the lines for carrying status signals comprise a line for carrying a signal indicating a processor controller intervening in the local system bus transaction.

Claim 23

Dependent Claim 15 words

A local system bus as in claim 1, further comprising lines for carrying interrupt signals.

Claim 24

Dependent Claim 24 words

A local system bus as in claim 22, wherein the lines for carrying interrupt signals comprise a line for carrying an interrupt request signal.

Claim 25

Dependent Claim 24 words

A local system bus as in claim 22, wherein the lines for carrying interrupt signals comprise a line for carrying a non-maskable interrupt signal.

Claim 26

Dependent Claim 24 words

A local system bus as in claim 22, further comprising an additional line for carrying a signal for resetting the micro-processor based computer system.

Claim 27

Dependent Claim 20 words

A local system bus as in claim 25, further comprising an additional line for carrying a local processor reset signal.

Claim 28

Dependent Claim 26 words

A local system bus as in claim 1, wherein the lines for carrying arbitration signals comprise a line for carrying a local system bus request signal.

Claim 29

Dependent Claim 31 words

A local system bus as in claim 1, wherein the lines for carrying arbitration signals comprise a line for carrying a local system bus grant signal to one of the controllers.

Claim 30

Dependent Claim 39 words

A local system bus as in claim 1, wherein the lines for carrying arbitration signals comprise a line for carrying an acknowledge signal indicating whether the local system bus is given up in response to a bus hold request.

Claim 31

Dependent Claim 18 words

A local system bus as in claim 1, further comprising lines for carrying signals supporting a distributed arbitration.

Claim 32

Dependent Claim 19 words

A local system bus as in claim 1, wherein each local system bus transaction comprises a sequence of phases.

Claim 33

Dependent Claim 19 words

A local system bus as in claim 31, wherein said phases comprise arbitration, command, address, data and status phases.

Claim 34

Dependent Claim 29 words

A local system bus as in claim 32, wherein the arbitration, command and address phases for a next transaction can start during the data phase of a present transaction.

Claim 35

Dependent Claim 18 words

A local system bus as in claim 33, wherein the local system bus operates at two bus speeds.

Claim 36

Dependent Claim 38 words

A local system bus as in claim 1, wherein the micro-processor based computer system comprises a peripheral control bus connected to the I/O bus and to each controller for programming peripheral devices connected to the local system bus.

Claim 37

Dependent Claim 152 words

A local system bus as in claim 35, wherein distributed interrupts are supported as follows: an interrupt request being generated onto the local system bus by an interrupt controller; an interrupt acknowledge sequence being generated by one of the controllers connected between the local system bus and the micro-processor and an interrupt vector being driven during the interrupt acknowledge; the interrupt vector being captured by every controller connected between the local system bus and the micro-processor; an interrupt signal generated by one of the controllers that is enabled by the captured interrupt vector being sent to an associated micro-processor, and a protection signal being generated by the enabled controller for preventing any of the controllers from acknowledging any subsequent interrupt request; an interrupt acknowledger being generated by the associated micro-processor to the enabled controller; and a prevention signal being released by the enabled controller in response to receiving of the interrupt knowledge.

Claim 38

Dependent Claim 30 words

A local system bus as in claim 36, wherein the interrupt vector is carried on the peripheral control bus to enable any of the controllers to capture the interrupt vector.

Claim 39

Dependent Claim 89 words

A local system bus as in claim 1, wherein an arbitration for control of the local system bus is as follows: signals being generated onto the local system bus by a cache controller that requires the local system bus; a selected bus owner being determined in response to the generated signals; the selected bus owner waiting for a current bus owner to relinquish the local system bus by driving a grant signal onto the local system bus; and the selected bus owner assuming control of the local system bus.

Claim 40

Dependent Claim 105 words

A micro-processor based computer system including at least a first micro-processor and a cache memory, a system memory, and input/output devices, the computer system comprising: a local system bus for connecting the micro-processor to the cache memory; an input/output bus for connecting to the input/output devices; a first controller for connecting the local system bus to the I/O bus; wherein the local system bus operates at a higher data rate than does the input/output bus; at least one cache controller connected between the first micro-processor and the local system bus; and a second cache controller connected between the local system bus and the system memory.

Claim 41

Dependent Claim 105 words

A micro-processor based computer system including at least a first micro-processor and a cache memory, a system memory, and input/output devices, the computer system comprising: a local system bus for connecting the micro-processor to the cache memory; an input/output bus for connecting to the input/output devices; a first controller for connecting the local system bus to the I/O bus; wherein the local system bus operates at a higher data rate than does the input/output bus; at least one cache controller connected between the first micro-processor and the local system bus; and a second cache controller connected between the local system bus and the system memory.

Claim 42

Dependent Claim 20 words

A computer system as in claim 39, wherein the input/output bus is one of an ISA, MCA or EISA bus.

Claim 43

Dependent Claim 33 words

A computer system as in claim 39, further comprising a peripheral control connected to the input/output bus and at least one cache controller for programming peripheral devices connected to the local system bus.

Claim 44

Dependent Claim 39 words

The computer system of claim 41, further comprising means for allowing a peripheral device connected to the local system bus to control a speed of data transfers to or from another peripheral device connected to the local system bus.

Claim 45

Dependent Claim 40 words

A computer system as in claim 39, wherein the first micro-processor has a first clocking scheme, and further comprising a second micro-processor having a second clocking scheme differing from the first clocking scheme and connected to the local system bus.

Claim 46

Dependent Claim 21 words

The computer system of claim 39, further comprising means for connecting at least a second micro-processor to the local system bus.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1999-05-14	1999-11-13	2000-05-14	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2003-05-14	2003-11-13	2004-05-14	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2007-05-14	2007-11-13	2008-05-14	$7700.00	Window Closed / Lapsed

Open high speed bus for microcomputer system

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