High speed interconnect unit for digital data processing system

Claim 1

An interconnect unit for connection to a system bus in a digital data processing system including a memory for storing information and a processor means for controlling the system, said interconnect unit transferring information between the memory over said system bus and an external device over an external bus, said external bus including bidirectional information transfer lines for transferring information signals, antiparallel unidirectional direction control lines having selected conditions for transferring direction control signals identifying a direction of transfer of information and antiparallel unidirectinal synchronization lines for transferring synchronization signals, in response to commands from the processor means, said interconnect unit including: A. system transfer means for connection to said system bus for transferring information to or from said memory, B. external device transfer means including means for connection to said external bus for transmitting and receiving information over said external bus, and further including information transfer means connected to said system transfer means and for connection to said information transfer lines for transferring information between said system transfer means and said information transfer lines, said direction control lines asserting a signal on one of said direction control lines and receiving a signal on a second of said direction control lines identifying a condition of the direction of transfer of information over said information transfer lines, said synchronization lines asserting a signal on one of said synchronization lines and receiving a signal on a second of said synchronization lines to synchronize the transfer of information over said information transfer lines, and C. control means for operational control of the interconnect unit in transferring information over said information transfer lines, said control means including a first register enabling the transmission and reception of the direction control signals over the respective direction control lines to identify the direction of transfer, said control means enabling the selection of transmission or reception of information signals over said information transfer lines responsive to the condition of said direction control signals, and said control means enabling a synchronization signal to identify: I. when information signals are being transferred over said information transfer lines when said direction control signals indicate that information is being transferred to said external device to enable said external device to receive said information signals, or II. when information signals have been received from said information transfer lines when said direction control signals indicate that information is being transferred from said external device.