Data processing machine suitable for high-speed processing

Claim 1

A data processing machine comprising a first memory for storing destination addresses designating locations of instructions used in a data processing, a second memory accessed with the destination addresses output from said first memory and storing said instructions therein, an arithmetic means for executing an arithmetic operation in accordance with the instructions read out of said second memory, a third memory for temporarily storing first data read out from said second memory which has reached said third memory in advance of a second data which is needed together with said first data for a dyadic operation, until said second data reaches said third memory, a fourth memory for storing data read out from said third memory waiting to be processed in said arithmetic means and data waiting to be transferred to the outside of said data processing machine, interface means for receiving data to be transferred to said first memory from the outside of said data processing machine and for transferring data in said fourth memory to the outside of said data processing machine, and bus means for coupling said first to fourth memories and said arithmetic means into a ring shape, said fourth memory including a data queue memory means for storing data to be used in an operation of an instruction which does not increase the number of data to be stored back in said fourth memory, a generator queue memory means for storing data to be used in an operation of an instruction which increases the number of data to be stored back in said fourth memory, and a means for monitoring the amount of data in said data queue memory means and inhibiting an output of said generator queue memory means to said arithmetic means when said monitored amount exceeds a predetermined amount.