US5237676A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device
Assignee: Lenovo Singapore Pte Ltd
•
Filing: 1989-01-13
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Granted: 1993-08-17
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Expires: 2009-01-13
Abstract
Abstract A computer system bus includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.
Inventors
- 👤 Ravi K. Arimilli
- 👤 Sudhir Dhawan
- 👤 George A. Lerom
- 👤 James O. Nicholson
- 👤 David W. Siegel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:42
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
180 words
A method for transferring data on a computer system bus between a master subsystem and a slave subsystem, comprising the steps of; beginning a clock cycle on a first clock signal line; determining whether the slave subsystem can support a high speed data transfer, wherein said determining step comprises the steps of; the slave subsystem indicating on a selected control line whether it can support high speed data transfer, and the master subsystem detecting the selected control line and determining whether the slave subsystem can support high speed data transfer based on the indication thereon; if the slave subsystem desired to terminate the transfer of data under control of the second clock signal line, changing the indication on the selected control line and in response to the changed indication, the master subsystem terminating data transfer under control of the second clock signal line; if the master subsystem desires to terminate the transfer of data under control of the second clock signal line, ceasing generating the high speed clock signal; and completing the clock cycle on the first clock signal line.
Claim 2
Independent Claim
180 words
A method for transferring data on a computer system bus between a master subsystem and a slave subsystem, comprising the steps of; beginning a clock cycle on a first clock signal line; determining whether the slave subsystem can support a high speed data transfer, wherein said determining step comprises the steps of; the slave subsystem indicating on a selected control line whether it can support high speed data transfer, and the master subsystem detecting the selected control line and determining whether the slave subsystem can support high speed data transfer based on the indication thereon; if the slave subsystem desired to terminate the transfer of data under control of the second clock signal line, changing the indication on the selected control line and in response to the changed indication, the master subsystem terminating data transfer under control of the second clock signal line; if the master subsystem desires to terminate the transfer of data under control of the second clock signal line, ceasing generating the high speed clock signal; and completing the clock cycle on the first clock signal line.
Claim 3
Dependent Claim
42 words
The method of claim 1 wherein, if the slave subsystem can support a high speed data transfer, transferring at least one item under control of the second clock signal line, and transferring a last data item during said clock cycle completing step.
Claim 4
Independent Claim
123 words
A method for transferring data on a computer system bus between a master subsystem and a slave subsystem, comprising the steps of; beginning a clock cycle on a first clock signal line; determining whether the slave subsystem can support a high speed data transfer; if the slave subsystem can support a high speed data transfer, generating at least one high speed clock cycle on a second clock signal line and transferring data between the slave and master subsystems under control of the second clock signal line; if the master subsystem desires to terminate the transfer of data under control of the second clock signal line, ceasing generating the high speed clock signal; and completing the clock cycle on the first clock signal line.
Claim 5
Independent Claim
123 words
A method for transferring data on a computer system bus between a master subsystem and a slave subsystem, comprising the steps of; beginning a clock cycle on a first clock signal line; determining whether the slave subsystem can support a high speed data transfer; if the slave subsystem can support a high speed data transfer, generating at least one high speed clock cycle on a second clock signal line and transferring data between the slave and master subsystems under control of the second clock signal line; if the master subsystem desires to terminate the transfer of data under control of the second clock signal line, ceasing generating the high speed clock signal; and completing the clock cycle on the first clock signal line.
Claim 6
Dependent Claim
56 words
The method of claim 3, wherein said determining step comprises the steps of: the slave subsystem indicating on a selected control line whether it can support high speed data transfer; and the master subsystem detecting the selected control line and determining whether the slave subsystem can support high speed data transfer based on the indication thereon.
Claim 7
Dependent Claim
58 words
The method of claim 4, further comprising the steps of: if the slave subsystem desires to terminate the transfer of data under control of the second clock signal line, changing the indication on the selected control line; and in response to the changed indication, the master subsystem terminating data transfer under control of the second clock signal line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-16 | 1997-02-15 | 1997-08-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-16 | 2001-02-15 | 2001-08-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-16 | 2005-02-15 | 2005-08-17 | $7700.00 | Window Closed / Lapsed |