Microprogrammable peripheral processing system

Claim 2

A microprogrammed peripheral processor coupled to a first interface and being operative to control the operation of at least one input/output device coupled to a second interface in response to command signals received from said first interface and for transferring information signals between said first and second interfaces involving said input/output device, said peripheral processor comprising: microprogram control means, said control means including; storage means having a plurality of storage locations for storing a plurality of microinstruction sequences, each having a plurality of microinstructions, branch control means including a plurality of input terminals coupled to receive a plurality of signals to be tested and coupled to said storage means for conditioning said storage means to branch to different ones of said sequences in accordance with said signals and decoding means coupled to said storage means for generating control signals in response to said microinstructions read out from said storage means during a cycle of operation; bidirectional data transfer means for transferring information signals coupled to said first and second interfaces; sequence control means for generating control signals coupled to said data transfer means and to said microprogram control means and, said branch control means in response to signals applied to different ones of said terminals representative of a command code to condition said storage means to branch to one of said sequences, said decoding means being operative to generate control signals in response to decoding microinstructions of said one sequence for application to said sequence control means, said sequence control means being conditioned by said signals to generate said signals for controlling the subsequent transfer of information signals through said data transfer means at a rate independent of the operating rate of said microprogram control means.

Claim 3

The peripheral processor of claim 1 wherein said sequence control means includes; a plurality of bistable devices connected to switch state in response to predetermined ones of said control signals from said microprogram control means and wherein said one of said routines includes at a specified point therein a predetermined said plurality of bistable devices to predetermined states for controlling said transfer of information signals.

Claim 4

The processor of claim 2 wherein said predetermined type of microinstruction is an input/output type microinstruction including a plurality of fields, one of said plurality corresponding to a sequence field coded to establish which ones of said plurality of bistable devices are to be switched to their binary ONE states for execution of the operation specified by said command code.

Claim 5

The processor of claim 1 wherein said storage means includes a read only storage element.

Claim 6

The processor of claim 1 wherein one of said input terminals of said branch control means couples to said sequence control means, said branch control means in the absence of a predetermined signal from said sequence control means being operative to condition said storage means to repeat cycling through a predetermined microinstruction sequence, said one of said input terminals of said branch control means being operative upon receipt of said predetermined signal from said control sequencing means indicating completion of said data transfer to inhibit said storage means from repeating cycling through said predetermined microinstruction sequence.

Claim 7

The processor of claim 5 wherein said sequence includes two branch type microinstructions coded to contain branch addresses and test conditions which provide a two microinstruction loop until one of said test conditions is satisfied.

Claim 8

The processor of claim 5 wherein said sequence control means further includes; cycle control means coupled to different ones of said bistable means, said cycle control means including a plurality of bistable means, said plurality of bistable means of said cycle control means being conditioned by said bistable means to switch state in a predetermined sequence in response to signals indicating the occurrence of certain hardware events for generating signals defining different sequences of operations for said processor during said transfer.

Claim 9

The processor of claim 5 wherein said one of said input terminals of said branch control means is operative in response to said predetermined signal to cause said storage means to branch to another microinstruction sequence to test the results of said transfer and said branch control means in accordance with signals representative of said results applied to other ones of said input terminals causing said storage means to sequence to a predetermined routine of microinstructions for processing a next command code.

Claim 10

The processor of claim 7 wherein one of said plurality of bistable means of said cycle control means is connected to receive said predetermined signal indicating an end of said data transfer, said one bistable means being operative to switch from a first state to a second state applying a signal to said one of said input terminals, said branch control means being conditioned by signals from said decoding means decoding a microinstruction in said sequence coded to test the state of said signal to inhibit said microprogram control storage means from repeating cyclIng through said sequence when said one bistable means is in said second state.

Claim 11

The processor of claim 1 wherein said bidirectional data transfer means includes: a plurality of buffer registers, coupled in series to transfer bidirectionally information byte serially therebetween; and, circuit means coupled to different ones of said buffer registers and to said sequence control means, said circuit means being conditioned by said sequence control means to enable selectively said buffer registers in a predetermined manner to operate said data transfer means in a plurality of different modes.

Claim 12

The processor of claim 10 wherein said sequence control means includes a transfer in flip-flop and transfer out flip-flop coupled to said circuit means, said circuit means being operative to establish the direction of transfer for first and second groups of said plurality of buffer registers in accordance with the states of said transfer flip-flops.

Claim 13

The processor according to claim 11 wherein said first group includes registers designated A, B and C and said second group includes registers designated D, E and F, said circuit means being responsive to said transfer-in flip-flop when a binary ONE and a binary ZERO respectively to condition said first group so as transfer bytes from said C register to said A register and from said A register to said C register and said circuit means being responsive to said transfer-out flip-flop when a binary ONE and a binary ZERO respectively to condition said second group to transfer bytes from said D register to said F register and from said F register to said D register.

Claim 14

The processor according to claim 12 wherein signals corresponding to the states of said transfer-in and transfer-out flip-flops are used to define a plurality of submodes of operation in accordance with the states of certain ones of said control sequence flip-flops.

Claim 15

The processor according to claim 13 wherein during a first submode of operation, said processor sequence control means includes first logic control circuits for generating signals for enabling a transfer of information bytes into said processor from said first and second interfaces through said first and second groups of registers.

Claim 16

The processor according to claim 2 further including: arithmetic and logic unit coupled to said second interface and to said data transfer means; and, read/write storage coupled to said arithmetic and logic unit and to said data transfer means, said sequence control means including second logic control circuits operative to apply said signals for conditioning said arithmetic and logic unit and said read/write storage to perform sequences of operations required for processing and storage of said byte signals respectively.

Claim 17

A peripheral subsystem including a peripheral processor coupled to a peripheral subsystem bus and to at least one peripheral device, said processor operative for controlling the operation of said one peripheral device coupled to a device level interface for a transfer of byte signals between said peripheral subsystem bus and device level interface in response to commands applied to said subsystem bus, said peripheral processor comprising: a peripheral subsystem interface portion; a microprogram control means, said control means including; addressable control memory for storing a plurality of microinstructions, branch control means having a number of test inputs and coupled to said control memory for conditioning said control memory to branch to said microinstructions in accordance with signals applied to said inputs, and decoding means coupled to said control memory for generating control signals in response to said microinstructions read out from said control memory; buffer register and control means coupled to said peripheral subsystem interface portion; an arithmetic and logic unit coupled to said microprogram control means and tO said buffer register and control means; a device level interface portion coupled to said device level interface; read/write storage coupled to said buffer register and control means and to said arithmetic and logic unit; adapter control circuits coupled to said device level interface portion, to said buffer register and control means and to said arithmetic and logic unit; and, sequence control means for generating subcommand control signals and being coupled to said microprogram control means, said arithmetic and logic unit, said read/write storage, said adapter control circuits and to said buffer register and control means; said branch control means in response to command code signals corresponding to one of said commands applied from said bus applied to certain ones of said test inputs to condition said control memory to branch to a first sequence of microinstructions, said decoding means in response to microinstructions of said sequence being operative to generate control signals for conditioning said sequence control means to apply a predetermined set of said subcommand control signals for operatively connecting for operation said buffer register and control means, said arithmetic and logic unit, said read/write storage, and said adapter control circuits in a predetermined manner for performing transfers of byte signals required for the execution of said one command under the control of said sequence control means.

Claim 18

A peripheral subsystem including a peripheral processor coupled to a peripheral subsystem bus and to at least one peripheral device, said processor operative for controlling the operation of said one peripheral device coupled to a device level interface for a transfer of byte signals between said peripheral subsystem bus and device level interface in response to commands applied to said subsystem bus, said peripheral processor comprising: a peripheral subsystem interface portion; a microprogram control means, said control means including; addressable control memory for storing a plurality of microinstructions, branch control means having a number of test inputs and coupled to said control memory for conditioning said control memory to branch to said microinstructions in accordance with signals applied to said inputs, and decoding means coupled to said control memory for generating control signals in response to said microinstructions read out from said control memory; buffer register and control means coupled to said peripheral subsystem interface portion; an arithmetic and logic unit coupled to said microprogram control means and tO said buffer register and control means; a device level interface portion coupled to said device level interface; read/write storage coupled to said buffer register and control means and to said arithmetic and logic unit; adapter control circuits coupled to said device level interface portion, to said buffer register and control means and to said arithmetic and logic unit; and, sequence control means for generating subcommand control signals and being coupled to said microprogram control means, said arithmetic and logic unit, said read/write storage, said adapter control circuits and to said buffer register and control means; said branch control means in response to command code signals corresponding to one of said commands applied from said bus applied to certain ones of said test inputs to condition said control memory to branch to a first sequence of microinstructions, said decoding means in response to microinstructions of said sequence being operative to generate control signals for conditioning said sequence control means to apply a predetermined set of said subcommand control signals for operatively connecting for operation said buffer register and control means, said arithmetic and logic unit, said read/write storage, and said adapter control circuits in a predetermined manner for performing transfers of byte signals required for the execution of said one command under the control of said sequence control means.

Claim 19

The peripheral subsystem according to claim 16 wherein said sequence control means includes: command storage means, said command storage means including a plurality of bistable storage means connected to switch to predetermined states in response to said control signals for providing said predetermined set of subcommand control signals, and; cycle control means coupled to said command storage means, said cycle control means including a plurality of bistable storage elements selectively coupled to receive certain ones of said set of control signals from said plurality of bistable storage means and signals from different portions of said subsystem indicative the occurrence of certain hardware events, said plurality of bistaable storage means being operative to generate cycle control signals for defining different sequences of operations to be performed by said arithmetic and logic unit and said read/write storage during said execution of said one command.

Claim 20

The peripheral subsystem according to claim 17 wherein said processor further includes: data counter means coupled to said read/write storage and to said microprogram control means, said counter means including input means conditioned by control signals during said first sequence for loading said counter means selectively with a predetermined count indicative of the number of byte signals to be transferred between said interface portions and said counter means being coupled to said adapter control circuits, said counter means including circuit means being responsive to certain ones of said signals from said adapter control circuits indicative of the occurrence of transfers of byte signals to modify said count during the execution of said one command.

Claim 21

The subsystem according to claim 18 wherein said counter means further includes: decoder means being operative to generate an output control signal when said counter means has been modified to store a count indicating the completion of the transfer of said number of byte signals; and, wherein one of said inputs of branch control means is coupled to receive said output control signal, said branch control means being responsive to said output control signal to cause said control memory to discontinue sequencing through the microinstruction sequence under execution and begin execution of a subsequent microinstruction sequence for processing the results from executing said one command.

Claim 22

The subsystem of claim 17 wherein said peripheral subsystem interface portion iNcludes: a first plurality of bistable storage elements coupled to said microprogram control means, said first plurality of storage elements being conditioned to control the transfer of signals through said portion; and, interface sequence control means including a second plurality of bistable storage elements coupled to said microprogram control means, said control signals being operative to switch said second plurality of bistable storage elements to predetermined states to condition said subsystem interface portion for execution of said one command.

Claim 23

The subsystem of claim 20 wherein said first sequence of microinstructions includes an input/output type microinstruction which has a plurality of field portions including a first sequence field portion coded to define the states of said second plurality of bistable storage means of said peripheral subsystem interfaces and a second sequence field portion coded to define the states of a second plurality of bistable storage means of said sequence control means, said sequence control means being conditioned by said input/output type microinstruction to generate signals to switch said plurality of bistable storage means to predetermined states in accordance with said first and second sequence fields for conditioning said processor to execute said one command.

Claim 24

The subsystem of claim 21 wherein said peripheral subsystem portion includes counter means coupled to said microprogram control means and to said read/write storage and wherein said input/output type microinstruction further includes a sub op code field portion coded to define which one of said counter means is to be loaded with said predetermined count and a count field portion coded to define said predetermined number, said sequence control means being operative in response to said microinstruction to generate signals for loading a specified one with said number.

Claim 25

The subsystem of claim 21 wherein said first sequence of microinstructions further includes read/write store microinstructions and logic type microinstructions, and decoding means being operative in response to said microinstructions for generating signals for conditioning said read/write storage, said adapter control circuits, said one peripheral device and said arithmetic and logic unit for executing said one command.

Claim 26

The subsystem of claim 22 wherein said sub op code field portion of said input/output type microinstruction is coded as follows: 00 designates that said counter means of said peripheral subsystem portion is to be loaded from said read/write storage; 01 designates that said counter means of said peripheral subsystem portion is to be loaded from said microprogram control means; 10 designates that said data counter means is to be loaded from said read/write storage; and, 11 designates that said data counter means is to be loaded from said microprogram control means.

Claim 27

The subsystem of claim 22 wherein at least two of said plurality of bistable storage elements of said cycle control means are interconnected to form a trap counter, and wherein said input/output type microinstruction further includes a trap count field portion coded to specify a number of data byte signals received from said one peripheral device to be trapped during the execution of said one command, said decoding means of said microprogram control means being operative in response said microinstruction to generate signals for loading said trap counter with a bit representation of said trap count field portion.

Claim 28

The subsystem of claim 25 wherein said command code signals designating said one command applied to said subsystem bus coded to specify a read, a write or search operation involving said one peripheral device for conditioning said branch control means to have said control memory branch to different sequences of microinstructions, each including at specified points therein an input/output type microinstruction coded to cOndition said sequence control means to enable said processor to execute the operation specified.

Claim 29

A peripheral processor coupled to a first interface and being operative to control the operation of any one of a plurality of input/output devices coupled to a second interface in response receiving command signals including a command code byte requiring the transfer of information byte signals between said first and second interfaces involving a selected one of said input/output devices, said peripheral processor comprising: a microprogram control means, said control means including; an addressable control store, said control store including a plurality of storage locations for storing microinstructions, an address register connected to said control store for storing an address for referencing said locations during cycles of operation, branch and test control means coupled to said address register, said branch control means including input means for receiving signals from different portions of said processor, said branch control means being operative in accordance with the testing of said signals to modify the contents of said address register to cause said store to branch to a sequence of microinstructions, an output register connected to said control store for temporarily storing the microinstruction contents of a referenced location during each cycle of operation, and decoding means coupled to said output register and operative to generate control signals in response to decoding certain portions of said microinstruction contents; bidirectional data transfer means, said transfer means having a plurality of inputs and output data paths, one input and output path being coupled to said first and second interface; arithmetic and logic means including; an arithmetic and logic unit having a first operand input and a second operand input and operative to perform a predetermined number of arithmetic and logic operations upon byte signals applied as operands to said first and second inputs and first and second input multiplex circuit means coupled to said first and second inputs respectively, each of said multiplex circuit means having an output and a plurality of inputs, said inputs being connected to receive byte signals from a corresponding number of sources and including circuit means for selecting signals from one of said sources to be applied to said output, at least one of said inputs of each of said input multiplex circuit means being connected to a predetermined one of output data paths and result circuit means coupled to said unit for generating signals indicating the results of operations performed on said operands; read/write storage means including plurality of storage locations for storing control and data bytes as required for execution of said commands, said storage means further including data input gating means coupled to predetermined ones of outputs of said data transfer means, control circuit means connected to said data input means and operative to generate signals for selecting which one of said outputs is to apply signals to said storage means, and output register means connected to store temporarily signals read out from an addressed one of said locations, said output register means being connected to said input multiplex circuit means; and, sequence control means coupled to said output register of said control store, said data transfer means and said read/write storage means; said microprogram branch control input means being coupled to said result circuit means and conditioned by the results of testing of said command code byte to cause said store to branch to a predetermined sequence of microinstructions, said decoding means being operative upon read out of microinstructions of said predetermined sequence to generate control signals, said sequence control means being conditioned by said control signals to apply signals to said data transfer means, said read/write sTorage control circuit means and to said input multiplex circuit means for subsequently enabling the transfer byte signals through said data transfer means to said first and second interfaces, to said arithmetic and logic means and to said read/write storage means as defined in accordance with said command code, said transfer proceeding under the control of said sequence control means at a rate established in accordance with said selected one of said input/output devices independently of the operating rate of said microprogram control means thereby making said control means available for the performance of operations unrelated to said transfer.

Claim 30

A peripheral processor coupled to a first interface and being operative to control the operation of any one of a plurality of input/output devices coupled to a second interface in response receiving command signals including a command code byte requiring the transfer of information byte signals between said first and second interfaces involving a selected one of said input/output devices, said peripheral processor comprising: a microprogram control means, said control means including; an addressable control store, said control store including a plurality of storage locations for storing microinstructions, an address register connected to said control store for storing an address for referencing said locations during cycles of operation, branch and test control means coupled to said address register, said branch control means including input means for receiving signals from different portions of said processor, said branch control means being operative in accordance with the testing of said signals to modify the contents of said address register to cause said store to branch to a sequence of microinstructions, an output register connected to said control store for temporarily storing the microinstruction contents of a referenced location during each cycle of operation, and decoding means coupled to said output register and operative to generate control signals in response to decoding certain portions of said microinstruction contents; bidirectional data transfer means, said transfer means having a plurality of inputs and output data paths, one input and output path being coupled to said first and second interface; arithmetic and logic means including; an arithmetic and logic unit having a first operand input and a second operand input and operative to perform a predetermined number of arithmetic and logic operations upon byte signals applied as operands to said first and second inputs and first and second input multiplex circuit means coupled to said first and second inputs respectively, each of said multiplex circuit means having an output and a plurality of inputs, said inputs being connected to receive byte signals from a corresponding number of sources and including circuit means for selecting signals from one of said sources to be applied to said output, at least one of said inputs of each of said input multiplex circuit means being connected to a predetermined one of output data paths and result circuit means coupled to said unit for generating signals indicating the results of operations performed on said operands; read/write storage means including plurality of storage locations for storing control and data bytes as required for execution of said commands, said storage means further including data input gating means coupled to predetermined ones of outputs of said data transfer means, control circuit means connected to said data input means and operative to generate signals for selecting which one of said outputs is to apply signals to said storage means, and output register means connected to store temporarily signals read out from an addressed one of said locations, said output register means being connected to said input multiplex circuit means; and, sequence control means coupled to said output register of said control store, said data transfer means and said read/write storage means; said microprogram branch control input means being coupled to said result circuit means and conditioned by the results of testing of said command code byte to cause said store to branch to a predetermined sequence of microinstructions, said decoding means being operative upon read out of microinstructions of said predetermined sequence to generate control signals, said sequence control means being conditioned by said control signals to apply signals to said data transfer means, said read/write sTorage control circuit means and to said input multiplex circuit means for subsequently enabling the transfer byte signals through said data transfer means to said first and second interfaces, to said arithmetic and logic means and to said read/write storage means as defined in accordance with said command code, said transfer proceeding under the control of said sequence control means at a rate established in accordance with said selected one of said input/output devices independently of the operating rate of said microprogram control means thereby making said control means available for the performance of operations unrelated to said transfer.

Claim 31

The processor of claim 27 wherein said sequence control means includes: a plurality of bistable devices connected to switch state in response to predetermined ones of said control signals from said microprogram control means and wherein said one of said routines includes at a specified point therein a predetermined type of microinstruction for initially presetting said plurality of bistable devices to predetermined states for controlling said transfer of information signals.

Claim 32

The processor of claim 28 wherein said predetermined type of microinstruction is an input/output type microinstruction including a plurality of fields, one of said plurality corresponding to a sequence field coded to establish which ones of said plurality of bistable devices are to be switched to their binary ONE states for execution of the operation specified by said command code.

Claim 33

The processor of claim 29 wherein said sequence control means further includes; cycle control means coupled to different ones of said bistable devices, said cycle control means including a plurality of bistable means, said plurality of bistable means of said cycle control means being conditioned by said bistable devices to switch state in a predetermined sequence in response to signals indicating the occurrence of certain hardware events for generating signals defining different sequences of operations for said processor during said transfer.

Claim 34

The processor of claim 30 wherein said branch control means couples to said sequence control means, said branch control means including input means which in the absence of a predetermined signal from said sequence control means being operative to condition said storage means to repeat execution of a predetermined microinstruction sequence, said input means of said branch control means being operative upon receipt of said predetermined signal from said control sequencing means indicating completion of said data transfer to inhibit said microprogram control means from repeating execution of said predetermined microinstruction sequence.

Claim 35

The processor of claim 31 wherein one of said plurality of bistable means of said cycle control means is connected to receive said predetermined signal indicating an end of said data transfer, said one bistable means being operative to switch from a first state to a second state, said branch control means upon executing a microinstruction in said sequence coded to test the state of said one bistable means to inhibit said microprogram control means from repeating execution of said sequence when said one bistable means is in said second state.

Claim 36

The processor of claim 32 wherein said processor further includes: a peripheral interface portion coupled to said first interface and said data transfer input and output paths, said interface portion including; a first plurality of bistable storage elements coupled to said microprogram control means, said first plurality of storage elements being conditioned to control the transfer of signals througsaid portion; and, interface sequence control means including a second plurality of bistable storage elements coupled to said microprogram control means, said control signals being operative to switch said second plurality of bistable storage elements to predetermined states to condition said subsystem interfAce portion for execution of said one command.