Input/output controller

Claim 2

In a digital system, an input/output controller for controlling the real time transfer of individual words of blocks of data between a processor and a plurality of input/output channels, each of said input/output channels including at least one peripheral device selectively connected to said processor by said input/output controller, each block of data being associated with an individual input/output channel, the input/output controller comprising: a. a plurality of storage means in said controller, each associated with one of the plurality of input/output channels, for storing digital signals from the processor to be used in controlling the transfer of data between the processor and the plurality of input/output channels; each of said plurality of storage means comprising a first register for storing the beginning address in the input/output channel for the transfer of the block of data, a second register for storing the beginning address in the processor for the transfer of the block of data, and a third register for storing the number of words in the block of data to be transferred; b. first control means for controlling when data is to be transferred between the processor and each of the plurality of input/output channels, said first control means being operably controlled from the processor; c. second control means operably connected to said first control means and to the plurality of input/output channels for selecting one of the plurality of input/output channels for the transfer of each individual word of data according to a predetermined priority; d. address generating means operably connected to said plurality of storage means and to at least one of said control means for generating addresses both for the selected input/output channel and for the processor to be used for the transfer of each individual word of data; e. means for initiating the transfer of one word of data directly between the processor and the selected input/output channel, said means being operably coupled to receive signals from the processor and the selected input/output channel which indicate readiness to transfer one word of data; f. detecting means operably coupled to said plurality of storage means for detecting the completion of the transfer of a block of data between the processor and the associated input/output channel. g. a plurality of counter means, each associated with one of the plurality of input/output channels, for counting the number of words in the block of data for the associated input/output channel that have been transferred; and h. adder means coupled to said first registers, said second reigsters and each of said plurality of counter means for adding the beginning address of the input/output channel to the number of words that have been transferred to obtain the address in the selected input/output channel to be used for the transfer of the current word of data, and for adding the beginning address in the processor to the number of words that have been transferred to obtain the address in the processor to be used for the transfer of the current word of data.

Claim 3

An input/output controller as claimed in claim 1 wherein said detecting means comprises: comparison means coupled to said third registers and to said plurality of counter means for comparing the number of words in the block of data to be transferred with the number of words that have been transferred thereby to detect the completion of the transfer of the block of data.

Claim 4

An input/output controller as claimed in claim 2 wherein said detecting means further comprises: signal means coupled to said comparison means for sending a signal to the processor when the completion of the Transfer of the block of data is detected.

Claim 5

An input/output controller as claimed in claim 1 wherein said first control means comprises: a. first means operably controlled from the processor for initiating data transfer; b. second means coupled to said detecting means and to the processor for terminating data transfer in response to signals from said detecting means or from the processor; and c. third means operably controlled from the processor for repetitively transferring a block of data.

Claim 6

In a digital system, an input/output controller for controlling the real time transfer of individual words of blocks of data between a processor and a plurality of input/output channels, each of said input/output channels including at least one peripheral device selectively connected to said processor by said input/output controller, each block of data being associated with an individual input/output channel, said input/output controller comprising: a. a plurality of first storage means in said controller, each associated with one of the plurality of input/output channels, each of said plurality of first storage means holding the beginning input/output channel address for the transfer of the block of data; b. a plurality of second storage means in said controller, each associated with one of the plurality of input/output channels, each of said plurality of second storage means holding the beginning processor address for the transfer of the associated block of data; c. a plurality of third storage means in said controller, each associated with one of the plurality of input/output channels, each of said plurality of third storage means holding the number of words in the associated block of data to be transferred; d. a plurality of counter means, each associated with one of the plurality of input/output channels, for counting the number of words in the associated block of data that have been transferred; e. a plurality of first control means, each associated with one of the plurality of input/output channels, each of said plurality of first control means being operative to control when data is to be transferred between the processor and the associated input/output channel, each of said plurality of first control means being operably controlled from the processor; f. second control means operably connected to said plurality of first control means and to the plurality of input/output channels for selecting one of the plurality of input/output channels for the transfer of one word of data according to a predetermined priority; g. address generating adder means having a first mode wherein it is operably connected to said plurality of second storage means and to said plurality of counter means and is responsive to said first control means for adding the beginning processor address to the number of words that have been transferred to the selected input/output channel to get the processor address to be used for the transfer of a current word of data; and said adder means having a second mode wherein it is operably connected to said plurality of first storage means and to said plurality of counter means and is responsive to said second control means for adding the beginning address of the selected input/output channel to the number of words that have been transferred to the selected input/output channel to get the address in the selected input/output channel to be used for the transfer of a current word of data; h. means for initiating the transfer of one word of data directly between the processor and the selected input/output channel, said means being operably coupled to receive signals from the processor and the selected input/output channel which indicate readiness to transfer one word of data; and i. detecting means operably connected to said plurality of third storage means and to said plurality of counter means for comparing the number of words in the block of data for the selected input/output channel with the number of Words that have been transferred for the selected input/output channel and thereby detecting the completion of the transfer of the block of data.

Claim 7

In a digital system, an input/output controller for controlling the real time transfer of individual words of blocks of data between a processor and a plurality of input/output channels, each of said input/output channels including at least one peripheral device selectively connected to said processor by said input/output controller, each block of data being associated with an individual input/output channel, said input/output controller comprising: a. a plurality of first storage means in said controller, each associated with one of the plurality of input/output channels, each of said plurality of first storage means holding the beginning input/output channel address for the transfer of the block of data; b. a plurality of second storage means in said controller, each associated with one of the plurality of input/output channels, each of said plurality of second storage means holding the beginning processor address for the transfer of the associated block of data; c. a plurality of third storage means in said controller, each associated with one of the plurality of input/output channels, each of said plurality of third storage means holding the number of words in the associated block of data to be transferred; d. a plurality of counter means, each associated with one of the plurality of input/output channels, for counting the number of words in the associated block of data that have been transferred; e. a plurality of first control means, each associated with one of the plurality of input/output channels, each of said plurality of first control means being operative to control when data is to be transferred between the processor and the associated input/output channel, each of said plurality of first control means being operably controlled from the processor; f. second control means operably connected to said plurality of first control means and to the plurality of input/output channels for selecting one of the plurality of input/output channels for the transfer of one word of data according to a predetermined priority; g. address generating adder means having a first mode wherein it is operably connected to said plurality of second storage means and to said plurality of counter means and is responsive to said first control means for adding the beginning processor address to the number of words that have been transferred to the selected input/output channel to get the processor address to be used for the transfer of a current word of data; and said adder means having a second mode wherein it is operably connected to said plurality of first storage means and to said plurality of counter means and is responsive to said second control means for adding the beginning address of the selected input/output channel to the number of words that have been transferred to the selected input/output channel to get the address in the selected input/output channel to be used for the transfer of a current word of data; h. means for initiating the transfer of one word of data directly between the processor and the selected input/output channel, said means being operably coupled to receive signals from the processor and the selected input/output channel which indicate readiness to transfer one word of data; and i. detecting means operably connected to said plurality of third storage means and to said plurality of counter means for comparing the number of words in the block of data for the selected input/output channel with the number of Words that have been transferred for the selected input/output channel and thereby detecting the completion of the transfer of the block of data.