US4860200A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor interface device for coupling non-compatible protocol peripheral with processor
Assignee: Tektronix Inc
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Filing: 1988-01-11
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Granted: 1989-08-22
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Expires: 2008-01-11
Abstract
Abstract A device for rendering a data source compatible with a processor having a predetermined protocol for receiving information from peripheral devices, comprises a controller for receiving information from the data source and conducting the protocol with the processor to place the processor in a condition for receiving the information. A latch receives information from the controller and makes the information available to the processor when the processor is in a condition for receiving information.
Inventors
- 👤 Dennis L. Holmbo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:54
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
206 words
A device for rendering a data source in a daisy chain of peripheral devices compatible with a processor having a predetermined protocol for receiving information from the peripheral devices comprising: an interrupt controller having a first interrupt input from one of the peripheral devices in the daisy chain and a second interrupt input from the data source, the first interrupt input indicating whether an interrupt is being processed by one of the peripheral devices higher in hierarchy in the daisy chain and the second interrupt input indicating whether the data source has information for the processor and the priority of such information, and having an interrupt request output to the processor and an interrupt inhibit output to the first peripheral device in the daisy chain, the interrupt request output indicating to the processor according to the protocol that one of the peripheral devices, including the data source, has information and the interrupt inhibit output disabling the peripheral devices higher in hierarchy when the information from the data source has a high priority; and a vector latch for receiving an interrupt vector from the data source for transmittal to the processor, the vector latch transmitting the interrupt vector to the processor upon command from the interrupt controller.
Claim 2
Independent Claim
206 words
A device for rendering a data source in a daisy chain of peripheral devices compatible with a processor having a predetermined protocol for receiving information from the peripheral devices comprising: an interrupt controller having a first interrupt input from one of the peripheral devices in the daisy chain and a second interrupt input from the data source, the first interrupt input indicating whether an interrupt is being processed by one of the peripheral devices higher in hierarchy in the daisy chain and the second interrupt input indicating whether the data source has information for the processor and the priority of such information, and having an interrupt request output to the processor and an interrupt inhibit output to the first peripheral device in the daisy chain, the interrupt request output indicating to the processor according to the protocol that one of the peripheral devices, including the data source, has information and the interrupt inhibit output disabling the peripheral devices higher in hierarchy when the information from the data source has a high priority; and a vector latch for receiving an interrupt vector from the data source for transmittal to the processor, the vector latch transmitting the interrupt vector to the processor upon command from the interrupt controller.
Claim 3
Dependent Claim
344 words
An improved microprocessor system of the type having a processor coupled to a data bus, the processor having an interrupt input, and a plurality of compatible peripherals coupled to the data bus, the compatible peripherals each having an interrupt indicator output, an interrupt output and an interrupt enable input and being connected in an interrupt daisy chain such that the interrupt output of one compatible peripheral is connected to the interrupt enable input of the next compatible peripheral in the daisy chain, the interrupt output of the last compatible peripheral in the daisy chain being connected to the interrupt input of the processor, and the interrupt indicator outputs being connected together, the improvement comprising: a latch coupled to the data bus; an interrupt controller connected in the daisy chain and having an controller interrupt enable input connected to the interrupt output of one of the compatible peripherals, an interrupt indicator input connected to the interrupt indicator outputs, a processor interrupt output connected to the interrupt input of the processor with the interrupt output of the last compatible peripheral being disconnected from the interrupt input of the processor, a controller interrupt output connected to the next compatible peripheral in the daisy chain, a command output connected to the latch for transferring a data vector stored in the latch to the data bus for the processor, and a priority inhibit line connected to the interrupt enable input of the first compatible peripheral in the daisy chain; and a non-compatible peripheral having a priority status line and an interrupt request line connected to the interrupt controller, and having a data vector line connected to the latch for transferring an interrupt data vector from the non-compatible peripheral to the latch for transmission as the data vector to the processor; whereby when the priority line is enabled only an interrupt request from the non-compatible peripheral is processed by the processor, and when the priority line is disabled the highest interrupt request from all of the peripherals in the daisy chain, including the non-compatible peripheral, is processed by the processor.
Claim 4
Dependent Claim
344 words
An improved microprocessor system of the type having a processor coupled to a data bus, the processor having an interrupt input, and a plurality of compatible peripherals coupled to the data bus, the compatible peripherals each having an interrupt indicator output, an interrupt output and an interrupt enable input and being connected in an interrupt daisy chain such that the interrupt output of one compatible peripheral is connected to the interrupt enable input of the next compatible peripheral in the daisy chain, the interrupt output of the last compatible peripheral in the daisy chain being connected to the interrupt input of the processor, and the interrupt indicator outputs being connected together, the improvement comprising: a latch coupled to the data bus; an interrupt controller connected in the daisy chain and having an controller interrupt enable input connected to the interrupt output of one of the compatible peripherals, an interrupt indicator input connected to the interrupt indicator outputs, a processor interrupt output connected to the interrupt input of the processor with the interrupt output of the last compatible peripheral being disconnected from the interrupt input of the processor, a controller interrupt output connected to the next compatible peripheral in the daisy chain, a command output connected to the latch for transferring a data vector stored in the latch to the data bus for the processor, and a priority inhibit line connected to the interrupt enable input of the first compatible peripheral in the daisy chain; and a non-compatible peripheral having a priority status line and an interrupt request line connected to the interrupt controller, and having a data vector line connected to the latch for transferring an interrupt data vector from the non-compatible peripheral to the latch for transmission as the data vector to the processor; whereby when the priority line is enabled only an interrupt request from the non-compatible peripheral is processed by the processor, and when the priority line is disabled the highest interrupt request from all of the peripherals in the daisy chain, including the non-compatible peripheral, is processed by the processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-21 | 1993-02-20 | 1993-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-21 | 1997-02-20 | 1997-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-21 | 2001-02-20 | 2001-08-22 | $7700.00 | Window Closed / Lapsed |