US4048673A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cpu - i/o bus interface for a data processing system
Assignee: EMC Corp
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Filing: 1976-02-27
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Granted: 1977-09-13
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Expires: 1996-02-27
Abstract
Abstract There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure or interfacing means for interfacing with I/O means (bus structure). The I/O means includes improved CPU transceiver and peripheral device ransceiver apparatus. The device transceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU transceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data transmission means which maintains accurate processing of data regardless of propagation delay, distortion, data skewing, etc., due to varying transmission distances and inherent limitations of MOS, bipolar, and other technology.
Inventors
- 👤 Gardner Cox Hendrie
- 👤 Harold Springer Crafts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 05:50
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/122; G06F13/38; H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/45
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
311 words
In a data processing system including (a) CPU with digital circuitry, (b) a main memory interfacing with said CPU, (c) I/O means for connecting between said CPU and peripheral devices, and (d) a clock source, interface means contained within said CPU for interfacing with said I/O means, said interface means comprising: means for receiving pulses derived from said clock source and for deriving further pulses therefrom; means for normally establishing an input mode of said interface means and responsive to signals from said CPU for establishing an output mode of said interface means; a first I/O pad connected to said I/O means; first shift register means for (1) serially receiving a first byte of a two byte data word from said first I/O pad responsive to certain of said further derived pulses and to the operation of said establishing means establishing said input mode and (2) serially generating said first byte of another two byte data word onto said first I/O pad responsive to other of said further derived pulses and to the operation of said establishing means establishing said output mode; a second I/O pad connected to said I/O means; second shift register means for (1) serially receiving the second byte of said two byte data word from said second I/O pad responsive to said certain of said further derived pulses and to the operation of said establishing means establishing said input mode and (2) serially generating said second byte of said another data word onto said second I/O pad responsive to said other of said further derived pulses and to the operation of said establishing means establishing said output mode; and means for parallel transferring (1) said data word from said first and second shift register means to said digital circuitry and (2) said another data word from said digital circuitry to said first and second shift register means.
Claim 2
Dependent Claim
311 words
In a data processing system including (a) CPU with digital circuitry, (b) a main memory interfacing with said CPU, (c) I/O means for connecting between said CPU and peripheral devices, and (d) a clock source, interface means contained within said CPU for interfacing with said I/O means, said interface means comprising: means for receiving pulses derived from said clock source and for deriving further pulses therefrom; means for normally establishing an input mode of said interface means and responsive to signals from said CPU for establishing an output mode of said interface means; a first I/O pad connected to said I/O means; first shift register means for (1) serially receiving a first byte of a two byte data word from said first I/O pad responsive to certain of said further derived pulses and to the operation of said establishing means establishing said input mode and (2) serially generating said first byte of another two byte data word onto said first I/O pad responsive to other of said further derived pulses and to the operation of said establishing means establishing said output mode; a second I/O pad connected to said I/O means; second shift register means for (1) serially receiving the second byte of said two byte data word from said second I/O pad responsive to said certain of said further derived pulses and to the operation of said establishing means establishing said input mode and (2) serially generating said second byte of said another data word onto said second I/O pad responsive to said other of said further derived pulses and to the operation of said establishing means establishing said output mode; and means for parallel transferring (1) said data word from said first and second shift register means to said digital circuitry and (2) said another data word from said digital circuitry to said first and second shift register means.
Claim 3
Dependent Claim
103 words
In a CPU including microcode structure for a data processing system, a parallel/series digital word converter interfacing with I/O structure of said system comprising: shift register means for serially receiving a digital word from said I/O structure; first means responsive to commands from said microcode structure for parallel transferring said digital word from said shift register means to said CPU; second means responsive to other commands from said microcode structure for parallel transferring another digital word from said CPU to said shift register means; and said shift register means including output means for serially transmitting said another digital word to said I/O structure.
Claim 4
Dependent Claim
103 words
In a CPU including microcode structure for a data processing system, a parallel/series digital word converter interfacing with I/O structure of said system comprising: shift register means for serially receiving a digital word from said I/O structure; first means responsive to commands from said microcode structure for parallel transferring said digital word from said shift register means to said CPU; second means responsive to other commands from said microcode structure for parallel transferring another digital word from said CPU to said shift register means; and said shift register means including output means for serially transmitting said another digital word to said I/O structure.
Claim 5
Dependent Claim
46 words
In the CPU of claim 2, said parallel/series word converter including means responsive with operation of said output means for transmitting a clock burst, each state of said burst corresponding to, and synchronizing, at least one respective bit of said another digital word simultaneously transmitted therewith.
Claim 6
Dependent Claim
36 words
In the CPU of claim 2, said output means including means for pre-setting at least the first bit of said another digital word to establish the nature of said another digital word for said I/O structure.
Claim 7
Dependent Claim
45 words
In the CPU of claim 4, said parallel/series word converter including means for inserting all one's into said shift register means and means for determining the completion of serial reception of said digital word by detecting a zero shifted out from said shift register means.
Claim 8
Dependent Claim
55 words
In the CPU of claim 4, said shift register means comprising four four-bit shift registers, a first two of said registers arranged to receive and transmit the left byte of a sixteen bit digital word, and the second two of said registers arranged to receive and transmit the right byte of said sixteen bit word.
Claim 9
Dependent Claim
41 words
In the CPU of claim 6, said first two of said registers including multiplexing means for associating even bits with one of said first two of said registers and odd bits with the other of said first two of said registers.
Claim 10
Dependent Claim
42 words
In the CPU of claim 7, said second two of said registers including other multiplexing means for associating even bits with one of said second two of said registers and odd bits with the other of said second two of said registers.
Claim 11
Dependent Claim
88 words
In the CPU of claim 2, said converter further including: means for normally establising an input mode of said converter; means responsive to operation of said microcode structure for establishing an output mode of said converter; input means, operative during said input mode, for receiving a BUS clock burst from said I/O structure in synchronism with said digital word; means for converting said BUS clock burst into other clock signals; and means responsive to said other clock signals for shifting-in said digital word into said shift register means.
Claim 12
Dependent Claim
36 words
In the CPU of claim 9, said converter including: means, responsive to operation of said output mode establishing means for generating another BUS clock burst to said I/O structure in synchronism with said another digital word.
References Cited (Backward Citations)
US3742456A
Cited
US3863226A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-09-12 | 1981-03-14 | 1981-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-09-12 | 1985-03-14 | 1985-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-09-12 | 1989-03-14 | 1989-09-13 | $7700.00 | Window Closed / Lapsed |