Level converting bus extender with subsystem selection signal decoding enabling connection to microprocessor

Claim 1

In a microprocessor system, a bus extender arrangement is connected between a microprocesor controller and a plurality of subsystems, said bus extender arrangement comprising: said microprocessor controller including microprocessor means; first gate array means connected to said microprocessor means for converting a plurality of signals of said microprocessor means from a first logic level to a second logic level; bus extender means including a plurality of bus extender circuit means, each bus extender circuit means including first level converting means connected between said first gate array means and said corresponding subsystem for converting said plurality of signals from said first to said second logic level, and second level converting means connected between said corresponding subsystem and said first gate array means for converting said plurality of signals from said second logic level to said first logic level; said plurality of subsystems each including second gate array means, and each subsystem connected via said corresponding bus extender circuit means to said microprocessor means, one at a time, for transferring data between said microprocessor means and one of said subsystems; selection signal means connected between said first gate array means and said bus extender means for addressing one of said plurality of subsystems; and each of said bus extender circuit means further including decoding means connected to said first gate array means, said corresponding subsystem and to said second level converting means, said decoding means operated in response to said operation of said selection signal means to enable said corresponding subsystem to connect to said microprocessor means.