Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
625 words
A computer system including a plurality of data processing stations each including a signal processing portion which interchanges data with a random access memory portion having a plurality of addressable word locations, and each of which also includes a signal processing interrupt function and an interrupt input terminal therefore, word location accessing logic means responsive to a word address signal to access a selected random access memory word location, read/write control logic for controlling the reading of data from and the writing of data into said random access memory, and a distributive bus system interconnecting said plurality of data processing stations, comprising: a bus controller for generating, and a bus for distributing, a plurality of control signals including periodic halt signals for interrupting said signal processing of said data processing stations, a plurality of time sequential data processing station address signals occurring during each said halt signal, time sequential word address signals occurring during each said data processing station address signal, and read/write signals occurring during each said word address signal; first coupling means coupled to said bus system and to each said data processing station for simultaneously coupling said halt signals to said interrupt input terminal of each said data processing station for halting signal processing for the duration of each said halt signal; decoding means coupled to each of said data processing stations and to said bus system and responsive to said data processing station address signals, each of said decoding means generating a first output signal during those intervals in which that data processing station to which it is coupled is addressed and generating a second output signal during those intervals in which that data processing station to which it is coupled is not addressed; first gating means coupled to each of said data processing stations, to each of said decoding means and to said bus system and responsive to the simultaneous occurrence of said halt signal, said read/write signal and said first output signal from said decoding means to supply a read signal to said read/write control logic, and responsive to the simultaneous occurrence of said halt signal, said read/write signal and said second output signal from said decoding means to supply a write signal to said read/write control logic whereby said random access memory portion of that data processing station which is addressed is enabled for reading and said random access memory portion of those data processing stations which are not addressed are enabled for writing; second gating means coupled to each of said word location accessing logic means and to said bus system and responsive to the simultaneous occurrence of said halt signal and said word address siggic means and to said bus system and responsive to the simultaneous occurrence of said halt signal and said word address signals for accessing the corresponding random access memory word location whereby the word in the memory location so accessed is read from the random access memory portion of that data processing station which is addressed and the memory location so accessed in the random access memory of those data processing stations which are not addressed is made available for writing; and third gating means coupled to said random access memory portion of each of said data processing stations, to said decoding means and to said bus system and responsive to said decoding means for coupling each word read from said random access memory portion of that data processing station which is addressed to a particular portion of said bus system in response to said first output signal of said decoding means and for coupling each word on said particular portion of said bus system to said random access memory portion of those data processing stations which are not addressed for writing.
Claim 2
Dependent Claim
625 words
A computer system including a plurality of data processing stations each including a signal processing portion which interchanges data with a random access memory portion having a plurality of addressable word locations, and each of which also includes a signal processing interrupt function and an interrupt input terminal therefore, word location accessing logic means responsive to a word address signal to access a selected random access memory word location, read/write control logic for controlling the reading of data from and the writing of data into said random access memory, and a distributive bus system interconnecting said plurality of data processing stations, comprising: a bus controller for generating, and a bus for distributing, a plurality of control signals including periodic halt signals for interrupting said signal processing of said data processing stations, a plurality of time sequential data processing station address signals occurring during each said halt signal, time sequential word address signals occurring during each said data processing station address signal, and read/write signals occurring during each said word address signal; first coupling means coupled to said bus system and to each said data processing station for simultaneously coupling said halt signals to said interrupt input terminal of each said data processing station for halting signal processing for the duration of each said halt signal; decoding means coupled to each of said data processing stations and to said bus system and responsive to said data processing station address signals, each of said decoding means generating a first output signal during those intervals in which that data processing station to which it is coupled is addressed and generating a second output signal during those intervals in which that data processing station to which it is coupled is not addressed; first gating means coupled to each of said data processing stations, to each of said decoding means and to said bus system and responsive to the simultaneous occurrence of said halt signal, said read/write signal and said first output signal from said decoding means to supply a read signal to said read/write control logic, and responsive to the simultaneous occurrence of said halt signal, said read/write signal and said second output signal from said decoding means to supply a write signal to said read/write control logic whereby said random access memory portion of that data processing station which is addressed is enabled for reading and said random access memory portion of those data processing stations which are not addressed are enabled for writing; second gating means coupled to each of said word location accessing logic means and to said bus system and responsive to the simultaneous occurrence of said halt signal and said word address siggic means and to said bus system and responsive to the simultaneous occurrence of said halt signal and said word address signals for accessing the corresponding random access memory word location whereby the word in the memory location so accessed is read from the random access memory portion of that data processing station which is addressed and the memory location so accessed in the random access memory of those data processing stations which are not addressed is made available for writing; and third gating means coupled to said random access memory portion of each of said data processing stations, to said decoding means and to said bus system and responsive to said decoding means for coupling each word read from said random access memory portion of that data processing station which is addressed to a particular portion of said bus system in response to said first output signal of said decoding means and for coupling each word on said particular portion of said bus system to said random access memory portion of those data processing stations which are not addressed for writing.