US3810114A — Data processing system

Claim 1

Independent Claim 479 words

A data processing system comprising: a plurality of data processing units including an arithmetic operation unit, a memory unit and peripheral data processing units, said data processing units being connected in series by a signal line; a main bus assembly including a request bus, a master synchronization bus, a slave synchronization bus and a data bus for connecting said data processing units in parallel so as to effect exchange of data with each other; a main bus control unit for delivering a ''''who'''' signal to the first unit of said serially connected data processing units upon receipt of a request signal via said request bus, and which comprises a first NAND gate including a first input terminal connected to said request bus and a second input terminal connected to said master synchronization bus, a second NAND gate including an input terminal connected to said slave synchronization bus, a third NAND gate including a first input terminal connected to said master synchronization bus and a second input terminal connected to the output terminal of said second NAND gate, and a fourth NAND gate including a first input terminal connected to the output terminal of said first NAND gate, a second input terminal connected to the output terminal of said third NAND gate and a ''''who'''' signal output terminal connected to the input terminal of said first unit; a plurality of first interface circuits each of which is associated with said respective data processing units said interface circuits being connected to receive said ''''who'''' signal via said signal line, transmit the ''''who'''' signal to the immediately following data processing unit when a data processing unit receiving the ''''who'''' signal does not generate a request signal to said request bus for the use of said main bus assembly, prevent the ''''who'''' signal from being further transferred to the immediately following data processing unit when a data processing unit receiving the ''''who'''' signal has already generated a request signal to said request bus, and select a called data processing unit associated with the address signal given forth by the request signal generated by a data processing unit so as to connect a desired two data processing units by the main bus assembly; a supplementary bus assembly for connecting at least the arithmetic operation unit to the memory unit via a second interface circuit which is associated with said supplementary bus assembly for giving preference to one of the main and supplementary assemblies when said assemblies are supplied with the request signals for using the main and supplementary assemblies, and which is reached by the earlier one of said signals for executing the data change between the arithmetic operation unit and memory unit through the supplementary bus assembly independently of the operation of the main bus assembly when exchange of data takes place between the peripheral data processing units through the main bus assembly.

Claim 2

Dependent Claim 479 words

A data processing system comprising: a plurality of data processing units including an arithmetic operation unit, a memory unit and peripheral data processing units, said data processing units being connected in series by a signal line; a main bus assembly including a request bus, a master synchronization bus, a slave synchronization bus and a data bus for connecting said data processing units in parallel so as to effect exchange of data with each other; a main bus control unit for delivering a ''''who'''' signal to the first unit of said serially connected data processing units upon receipt of a request signal via said request bus, and which comprises a first NAND gate including a first input terminal connected to said request bus and a second input terminal connected to said master synchronization bus, a second NAND gate including an input terminal connected to said slave synchronization bus, a third NAND gate including a first input terminal connected to said master synchronization bus and a second input terminal connected to the output terminal of said second NAND gate, and a fourth NAND gate including a first input terminal connected to the output terminal of said first NAND gate, a second input terminal connected to the output terminal of said third NAND gate and a ''''who'''' signal output terminal connected to the input terminal of said first unit; a plurality of first interface circuits each of which is associated with said respective data processing units said interface circuits being connected to receive said ''''who'''' signal via said signal line, transmit the ''''who'''' signal to the immediately following data processing unit when a data processing unit receiving the ''''who'''' signal does not generate a request signal to said request bus for the use of said main bus assembly, prevent the ''''who'''' signal from being further transferred to the immediately following data processing unit when a data processing unit receiving the ''''who'''' signal has already generated a request signal to said request bus, and select a called data processing unit associated with the address signal given forth by the request signal generated by a data processing unit so as to connect a desired two data processing units by the main bus assembly; a supplementary bus assembly for connecting at least the arithmetic operation unit to the memory unit via a second interface circuit which is associated with said supplementary bus assembly for giving preference to one of the main and supplementary assemblies when said assemblies are supplied with the request signals for using the main and supplementary assemblies, and which is reached by the earlier one of said signals for executing the data change between the arithmetic operation unit and memory unit through the supplementary bus assembly independently of the operation of the main bus assembly when exchange of data takes place between the peripheral data processing units through the main bus assembly.

Claim 3

Dependent Claim 210 words

The data processing unit according to claim 1 wherein the main bus assembly includes a request bus for conducting a request made by any of the aforesaid data processing units for the use of the main bus assembly to a main bus control unit; a ''''who'''' signal synchronization bus for applying a ''''who'''' signal synchronization signal indicating that the ''''who'''' signal delivered from the main bus control unit is stopped at any of the aforesaid data processing units which has already requested the use of the main bus assembly for exchanging the data with the desired other data processing unit; a data bus for effecting exchange of data between the aforesaid data processing units; an address bus for transmitting the address specified by a bus assembly-requesting unit to the selected called unit; a master synchronization bus for conducting a master synchronization signal showing the condition of a data processing unit requesting the use of the main bus assembly to said desired other data processing unit and also to the bus control unit; and a slave synchronization bus for supplying the bus assembly-requesting unit and bus control unit with a slave synchronization signal indicating that said desired other data processing unit has completed exchange of data with said bus assembly-requesting unit.

Claim 4

Dependent Claim 71 words

The data processing system according to claim 1 wherein the bus control unit includes a first gating circuit which generates a ''''who'''' signal upon receipt of a request for the use of the main bus assembly from any of the aforesaid data processing units and, upon completion of exchange of data between the bus assembly-requesting unit and said desired other data processing unit, shuts off the transmission of said ''''who'''' signal.

Claim 5

Dependent Claim 230 words

The data processing system according to claim 1 wherein the first interface circuit includes a flip-flop circuit which, when set by a bus assembly-requesting signal of its own associated data processing unit which desires the use of said assembly, supplies the request bus with said bus assembly-requesting signal; a second gating circuit which, when said flip-flop circuit is in a reset state when supplied with the ''''who'''' signal, transfers said ''''who'''' signal to the immediately following data processing unit and, when said flip-flop circuit is in a set state at the arrival of the ''''who'''' signal, prevents said ''''who'''' signal from being further transmitted from a data processing unit to the immediately following data processing unit; a third gating circuit which, when the flip-flop circuit receives said ''''who'''' signal in a set state, generates a master synchronization signal according to the internal timing signal of the data processing unit which has issued said ''''who'''' signal; a circuit generating a ''''who'''' signal synchronization signal showing that said ''''who'''' signal has been conducted exactly to the data processing unit which has actually requested the use of the main assembly; and a fourth gating circuit which, when the selected called data processing unit completes operation based on the data delivered from the bus assembly-requesting data processing unit, resets the flip-flop circuit by a slave synchronization signal generated at the time of said completion.

Claim 6

Dependent Claim 135 words

The data processing system according to claim 4 wherein the first interface circuit further includes a comparing circuit which compares its own address with the one delivered through the address bus from the main bus assembly-requesting data processing unit and, when both addresses synchronize with each other, generates a signal representing data being transmitted back to said bus assembly-requesting data processing unit from the selected called data processing unit; a fifth gating circuit for producing a signal to start the operation of the selected called data processing unit when the comparing circuit gives forth an output signal and the master synchronization bus is supplied with a master synchronization signal from the first interface circuit; and a sixth gating circuit for generating a slave synchronization signal when the selected called data processing unit completes its operation.

Claim 7

Dependent Claim 89 words

The data processing system according to claim 1 wherein the supplementary bus assembly includes a request bus which supplies the memory unit with a request made by at least the arithmetic operation unit for the use of the supplementary bus assembly; a memory completion bus which supplies the arithmetic operation unit with a memory completion signal delivered from the memory unit when it completes its operation; and an address bus for transmitting an address signal from at least the arithmetic operation unit to the selected called data processing unit.

Claim 8

Dependent Claim 111 words

The data processing system according to claim 1 wherein the supplementary bus assembly further includes an additional interface circuit which generates a signal requesting the use of the supplementary bus assembly upon receipt of a request made by the arithmetic operation unit for the use of said assembly and permits exchange of data between the arithmetic operation unit and memory unit until the memory completion bus gives forth a memory completion signal; and a further interface circuit formed at least in the memory unit to connect the memory unit to the arithmetic operation unit through the supplementary bus assembly upon arrival of a bus assembly-requesting signal from said arithmetic operation unit.

Claim 9

Dependent Claim 62 words

The data processing system according to claim 7 wherein the additional interface circuit includes a second flip-flop circuit which, when set by a bus assembly-requesting signal delivered from the arithmetic operation unit, supplies said signal to the supplementary request bus; and a gating circuit for resetting said second flip-flop circuit upon receipt of a memory completion signal from the memory completion bus.

Claim 10

Dependent Claim 137 words

The data processing system according to claim 7 wherein the further interface circuit includes a comparing circuit which compares its own address with the one delivered through the supplementary address bus from the arithmetic operation unit and, when both addresses correspond with each other, generates a signal representing data being delivered from the memory unit associated with said address; a first flip-flop circuit for storing according to an output from the comparing circuit a signal showing whether there is made any request for the use of the supplementary bus assembly; a second flip-flop circuit for storing a signal indicating the operating condition of the supplementary bus assembly; and a third flip-flop circuit for generating a pulse to start the operation of the memory unit when the first and second flip-flop circuits are brought to a reset state.

Claim 11

Dependent Claim 89 words

The data processing system according to claim 1 wherein the supplementary bus assemblies include a request bus for supplying the memory units with a signal requesting the use of said supplementary bus assemblies delivered from at least the arithmetic operation units; a memory completion bus for supplying the arithmetic operation units with a memory completion signal generated from the memory units when they complete operation; and an address bus for supplying the selected called unit with a signal denoting the address specified by at least the arithmetic operation units.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1977-05-06	1977-11-05	1978-05-07	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1981-05-06	1981-11-05	1982-05-07	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1985-05-06	1985-11-05	1986-05-07	$7700.00	Window Closed / Lapsed

Data processing system

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