Multiplexer

Claim 2

A multiplexer for interfacing between a computer and a plurality of transceivers to provide orderly transfer of data therebetween, said multiplexer comprising: control means for controlling the operation of said mutliplexer by predetermined control signals and clock pulses, an input gate connected to receive data from said computer and from said transceiver upon receipt of said predetermined control signals from said control means, register means connected to receive data from said input gate, said register means outputting said received data upon receipt of said clock pulses from said control means, output gate means operable to receive the output signals from said register means, said output gate means passing data to said computer and saId transceivers upon receipt of said predetermined control signals from said control means, and check means for comparing a sum indicative of data passed by said output gate means with a sum indicative of the data received by said input gate to determine whether each data transfer is correct.

Claim 3

The device of claim 1 wherein said output gate means comprises: a first output gate connected to receive signals from said register means and operable to pass said signals to said computer, and a second output gate connected to receive signals from said register means and operable to pass said signals to said transceivers and to said check means, and said check means including an adding means connected to said second output gate to add said data passed to said transceivers to provide said sum indicative of data passed by said output gate thereby.

Claim 4

The device of claim 1 wherein said control means comprises: a ''''READ'''' portion operable to control said multiplexer to transfer data from said transceivers to said computer, a ''''WRITE'''' portion operable to control said multiplexer to transfer data from said computer to said transceivers, each of said portions including a ''''START'''' flip-flop, a counter enable flip-flop, and a decade counter, a master oscillator connectable through each of said counter enable flip-flops to clock the appropriate one of said decade counters, means responsive to command signals from said computer for triggering an appropriate one of said portions, and means connected to each position of said counters for passing signals to control the actuation of said input gate, said register means, said output gate, and said check means.

Claim 5

The device of claim 1 further comprising: decode means connected to detect passage by said input gate of an end-of-transmission signal and operable to indicate such passage to said control unit, and reset means in said control unit responsive to detection of said end-of-transmission signal to reset said mutliplexer for another operation.

Claim 6

The device of claim 3 further comprising: a fixed length counter connected to be clocked by said master oscillator and operative upon acquiring a full count to cause said control unit to reset said multiplexer for another operation.

Claim 7

A control unit for controlling a multiplexer having gating means for gating passage of data including end of transmission and check sum data between a computer and a plurality of transceivers and having check means for comparing inputted data with passed data, said control unit comprising: a first decade counter, means connected to each position of said first decade counter operable upon clocking of said first counter to cause said gating means to transfer data from said computer to said transceivers, a second decade counter, means connected to each positon of said second counter and operable upon clocking of said second counter to cause said gating means to transfer data from said transceiver to said computer, a master oscillator connectable to clock said counters, coupling means responsive to command signals from said computer for coupling said oscillator to clock an appropriate one of said counters, and end of transmission flip-flop means actuated by said end of transmission data to pass said check sum data to said check means.

Claim 8

A control unit for controlling a multiplexer having gating means for gating passage of data including end of transmission and check sum data between a computer and a plurality of transceivers and having check means for comparing inputted data with passed data, said control unit comprising: a first decade counter, means connected to each position of said first decade counter operable upon clocking of said first counter to cause said gating means to transfer data from said computer to said transceivers, a second decade counter, means connected to each positon of said second counter and operable upon clocking of said second counter to cause said gating means to transfer data from said transceiver to said computer, a master oscillator connectable to clock said counters, coupling means responsive to command signals from said computer for coupling said oscillator to clock an appropriate one of said counters, and end of transmission flip-flop means actuated by said end of transmission data to pass said check sum data to said check means.

Claim 9

The device of claim 2 including: a decoder connected between said computer and said control means to detect said sum indicative of the data received by said input gate and signal said control means upon detecting said sum, said control means providing a signal to said check means upon receiving said sum detecting signal from said decoder to compare said sum indicative of data passed with said sum indicative of data received.