Multiple CPU control system

Claim 1

A logic system for controlling the access of plural central processing units (CPUs) on a local communication bus to a remote communication bus to avoid CPU deadlocks which may occur when plural CPUs on said local bus issue bus cycle requests requiring the use of same logic flow paths through intersystem link (ISL) units to said remote bus in a data processing system having plural communication busses each providing a common information path for plural data processing units including memory units, peripheral control units, ISL units and CPUs electrically interfacing therewith, and each of said busses are in electrical communication with an ISL unit, and ISL units in turn are in electrical communication in pairs, which comprises: (a) register means in a local ISL unit in electrical communication with said local bus for storing at the bus rate binary coded information received from said local bus; (b) bus cycle compare logic means in said local ISL unit and in electrical communication with said register means and said local bus, and responsive to ACK, NAK and WAIT signals received from said remote bus by way of a remote ISL unit for indicating the occurrences of equivalents and non-equivalents between binary coded information stored in said register means and binary coded information on said local bus; (c) mode control means in said local ISL unit and in electrical communication with said register means and said remote ISL unit for storing a NAK retry bit signal supplied by said local or said remote bus during an ISL configuration mode to indicate the presence of plural CPUs on said local bus; and (d) NAK logic control means responsive to said non-equivalents and said NAK retry bit signal for issuing a NAK signal to those of said plural CPUs having an access priority higher than that of a lowest priority one of said plural CPUs, thereby providing said lowest priority one CPU with access to said remote bus.