Bidirectional data communication system

Claim 1

A bidirectional data communication system which comprises: a head end unit including a central processing unit (CPU) for processing data to provide data signals, a clock signal generating circuit for generating original clock signals, a transmitting circuit for feeding out the data signals from the central processing unit as downstream data signals to a downstream channel using the original clock signals from the clock signal generating circuit, a phase compensating circuit coupled to receive the original clock signals and upstream data signals from a terminal unit, the original clock signals having a frequency that is a multiple of the frequency of the downstream data rate, and the phase compensating circuit including controllable frequency divider means coupled to receive the original clock signals, and means responsive to the upstream data signals for resetting the frequency divider means in accordance with the phase of the upstream data for compensating the original clock signals so as to provide phase compensated clock signals corresponding in phase to upstream clock signals contained in upstream data signals from a terminal unit, and a data reproducing circuit for reproducing upstream data signals from a terminal, said data reproducing circuit being responsive to the phase compensated clock signals from the phase compensating circuit for providing data outputs to the central processing unit that may be processed in the central processing unit despite timing variations in the upstream clock signals; and a number of terminal units each including a clock signal reproducing circuit for reproducing only the received original clock signals contained in the downstream signal from the head end unit, a data reproducing circuit for reproducing downstream data signals using the reproduced clock signal output of the clock signal reproducing circuit, a data processing unit for processing the output of the data reproducing circuit and providing upstream data signals to be fed out to the head end unit, and a transmitting circuit coupled to the data processing unit and clock signal reproducing circuit for transmitting the upstream data signals from the data processing unit to the head end unit containing the reproduced upstream clock signals from the clock signal reproducing circuit.