Data control circuit

Claim 2

A data control circuit (18) for controlling the shifting of a data word through a shift register (20 or 120), the circuit including an interval counter (38); means for applying clock pulses (29); a control register for storing format data (37); the circuit being characterized by: means (42) for supplying a first signal (INIT) to the interval counter for presetting the interval counter; first gate means (40) for controllably transmitting the clock pulses from the applying means to the interval counter; second gate means (30) for controllably transmitting the clock pulses from the applying means to the shift register; a selection circuit (35) responsive to the format data stored in the control register and to a first count state and subsequent sequential count states of the interval counter for producing a second signal (READY) to fully condition the first gate means in preparation for transmitting the clock pulses to the interval counter and for partially conditioning the second gate means in preparation for transmitting the clock pulses to the shift register; means (45) for supplying a synchronization signal to the fully conditioned first gate means for enabling the first gate means for transmitting the clock pulses to the interval counter and for supplying the synchronization signal to the partially conditioned second gate means for fully conditioning the second gate means in preparation for transmitting the clock pulses to the shift register; the fully conditioned second gate means being responsive to the format data and being enabled by an occurrence of a second count state and subsequent sequential count states of the interval counter for transmitting the clock pulses to the shift register; and the selection circuit (35) being responsive to the format data stored in the control register and to a third count state of the interval counter for inverting the second signal (READY) and thereby disabling the first and second gate means (40 and 30) from transmitting the clock pulses.

Claim 3

A data control circuit in accordance with claim 1 further characterized by a clock/sync generator (28) for producing the clock pulses being applied through the applying means (29) to the first and second gate means and for generating the synchronization signal being supplied through the supplying means (45) to the first and second gate means for controlling transmission of the clock pulses through the first and second gate means (40 and 30) to the interval counter (38) and the shift register (20 or 120), respectively.

Claim 4

A data control circuit in accordance with claim 1 or 2 further characterized by means (30, 35, 37, 40) for selectively shifting the data word in the shift register concurrently with occurrence of the synchronization signal.

Claim 5

A data transfer circuit (18) arranged for transferring a data word in parallel from a data bus (21) to a shift register (20) and serially from the shift register to a peripheral device (22); the transfer circuit including an interval counter (38); means (28) for applying clock pulses; a control register (37) for storing format data; the data transfer circuit characterized by: means (24) for applying a signal (TRANSFER) to the shift register and to the interval counter for loading the data word in parallel from the data bus into the shift register and for resetting the interval counter; first gate means (40) for controllably transmitting the clock pulses from the applying means to the interval counter; second gate means (30) for controllably transmitting the clock pulses from the applying means to the shift register; a selection circuit (35) responsive to the format data stored in the control register and to a first count state and subsequent sequential count states of the interval counter for producing a signal (READY) for fully conditioning the first gate means in preparation for transmitting the clock pulses to the interval counter and for partially conditioning the second gate means in preparation for transmitting the clock pulses to the shift register; means (45) for supplying a synchronization signal to the fully conditioned first gate means for enabling the first gate means to transmit the clock pulses to the interval counter and for supplying the synchronization signal to the partially conditioned second gate means for fully conditioning the second gate means in preparation for transmitting the clock pulses to the shift register; the fully conditioned second gate means being responsive to the format data and being enabled by a second count state and subsequent sequential count states of the interval counter for transmitting the clock pulses to the shift register, each clock pulse causing the shift register to shift a bit of the data word in serial to the peripheral device; and the selection circuit being responsive to the format data stored in the control register and to a third count state of the interval counter for inverting the signal (READY) and thereby disabling the first and second gate means from transmitting the clock pulses to the interval counter and to the shift register, respectively.

Claim 6

A data transfer circuit (18) arranged for transferring a data word in parallel from a data bus (21) to a shift register (20) and serially from the shift register to a peripheral device (22); the transfer circuit including an interval counter (38); means (28) for applying clock pulses; a control register (37) for storing format data; the data transfer circuit characterized by: means (24) for applying a signal (TRANSFER) to the shift register and to the interval counter for loading the data word in parallel from the data bus into the shift register and for resetting the interval counter; first gate means (40) for controllably transmitting the clock pulses from the applying means to the interval counter; second gate means (30) for controllably transmitting the clock pulses from the applying means to the shift register; a selection circuit (35) responsive to the format data stored in the control register and to a first count state and subsequent sequential count states of the interval counter for producing a signal (READY) for fully conditioning the first gate means in preparation for transmitting the clock pulses to the interval counter and for partially conditioning the second gate means in preparation for transmitting the clock pulses to the shift register; means (45) for supplying a synchronization signal to the fully conditioned first gate means for enabling the first gate means to transmit the clock pulses to the interval counter and for supplying the synchronization signal to the partially conditioned second gate means for fully conditioning the second gate means in preparation for transmitting the clock pulses to the shift register; the fully conditioned second gate means being responsive to the format data and being enabled by a second count state and subsequent sequential count states of the interval counter for transmitting the clock pulses to the shift register, each clock pulse causing the shift register to shift a bit of the data word in serial to the peripheral device; and the selection circuit being responsive to the format data stored in the control register and to a third count state of the interval counter for inverting the signal (READY) and thereby disabling the first and second gate means from transmitting the clock pulses to the interval counter and to the shift register, respectively.

Claim 7

A data transfer circuit (18) arranged for transferring a data word in serial from a peripheral device (122) to a shift register (120) and in parallel from the shift register to a data bus (121); the transfer circuit including an interval counter (38); means (28) for applying clock pulses; a control register (37) for storing format data; the data transfer circuit characterized by: first gate means (40) for controllably transmitting the clock pulses from the applying means to the interval counter; second gate means (30) for controllably transmitting the clock pulses from the applying means to the shift register; a selection circuit (35) responsive to the format data stored in the control register and to a first count state and subsequent sequential count states of the interval counter for producing a signal (READY) for fully conditioning the first gate means in preparation for transmitting the clock pulses to the interval counter and for partially conditioning the second gate means in preparation for transmitting the clock pulses to the shift register; means (45) for supplying a synchronization signal to the fully conditioned first gate means for enabling the first gate means to transmit the clock pulses to the interval counter and for supplying the synchronization signal to the partially conditioned second gate means for fully conditioning the second gate means in preparation for transmitting the clock pulses to the shift register; the fully conditioned second gate means being responsive to the format data and being enabled by a second count state and subsequent sequential count states of the interval counter for transmitting the clock pulses to the shift register, each clock pulse causing the shift register to shift in a bit of the data word in serial from the peripheral device; the selection circuit being responsive to the format data stored in the control register and to a third count state of the interval counter for inverting the signal (READY) and thereby disabling the first and second gate means from transmitting the clock pulses to the interval counter and to the shift register, respectively; and means (124) for applying a signal (TRANSFER) to the shift register and to the interval counter for transferring the data word in parallel from the shift register onto the data bus and for resetting the interval counter.

Claim 8

A data transfer circuit (18) arranged for transferring a data word in serial from a peripheral device (122) to a shift register (120) and in parallel from the shift register to a data bus (121); the transfer circuit including an interval counter (38); means (28) for applying clock pulses; a control register (37) for storing format data; the data transfer circuit characterized by: first gate means (40) for controllably transmitting the clock pulses from the applying means to the interval counter; second gate means (30) for controllably transmitting the clock pulses from the applying means to the shift register; a selection circuit (35) responsive to the format data stored in the control register and to a first count state and subsequent sequential count states of the interval counter for producing a signal (READY) for fully conditioning the first gate means in preparation for transmitting the clock pulses to the interval counter and for partially conditioning the second gate means in preparation for transmitting the clock pulses to the shift register; means (45) for supplying a synchronization signal to the fully conditioned first gate means for enabling the first gate means to transmit the clock pulses to the interval counter and for supplying the synchronization signal to the partially conditioned second gate means for fully conditioning the second gate means in preparation for transmitting the clock pulses to the shift register; the fully conditioned second gate means being responsive to the format data and being enabled by a second count state and subsequent sequential count states of the interval counter for transmitting the clock pulses to the shift register, each clock pulse causing the shift register to shift in a bit of the data word in serial from the peripheral device; the selection circuit being responsive to the format data stored in the control register and to a third count state of the interval counter for inverting the signal (READY) and thereby disabling the first and second gate means from transmitting the clock pulses to the interval counter and to the shift register, respectively; and means (124) for applying a signal (TRANSFER) to the shift register and to the interval counter for transferring the data word in parallel from the shift register onto the data bus and for resetting the interval counter.