Collector

Claim 2

A collector for a synchronous central processing unit (CPU) of a data processing system having program addressable registers, a memory, said CPU having a repertoire of instructions and a plurality of execution units, wherein each of said execution unit executes a different subset of the repertoire of instructions independently of and in parallel with the other execution units and each executes the instructions in the order in which instructions are received by each such execution unit, said CPU having means for issuing in program order instructions to the collector and to the execution unit capable of executing the issued instruction; each execution unit that executes any instructions that requires more than one clock period having associated with it an input stack for storing instructions awaiting execution by its associated execution unit in the order received, the number of clock periods required to execute each instruction differing such that the results of the execution of instructions of a given program by the instruction execution units are not produced in program order; the collector comprising: means for storing in program order instructions issued by the means for issuing instructions to the collector; result means associated with each of said execution units for storing a plurality of results of the execution of instructions by its associated execution unit in the order executed; a master safe store and a store stack for storing the results in program order of the execution of each instruction executed by the execution units; and collector control means responsive to the order in which instructions are stored in the means for storing in program order instructions for causing results stored in the result means associated with each execution unit to be stored in program order in the master safe store if the results change the contents of an addressable register and to be stored in the store stack in program order if the results are to be written into memory.

Claim 3

A collector as defined in claim 1 in which result means associated with each execution unit is a fifo stack.

Claim 4

A collector as defined in claim 2 in which the means for storing in program order instructions issued by the means for issuing instructions is a fifo stack.

Claim 5

A collector as defined in claim 3 in which the master safe store and store stack is a fifo stack.

Claim 6

In a central processing unit (CPU) of a synchronous digital data processing system having a memory, said CPU having program addressable registers, a repertoire of instructions, a plurality of execution units, wherein each of said execution unit executes a different subset of the repertoire of instructions independently of and in parallel with the other execution units and each executes the instructions in the order received, at least one of said execution units executing a subset of the instructions that can be executed in one clock period, the number of clock periods required to execute each instruction differing such that the results of the execution of instructions of a give program by the instruction execution units are not produced in program order, said CPU having means for issuing instructions in program order, said means for issuing instructions in program order issuing instructions to the execution unit capable of executing the issued instruction, the improvements comprising: an instruction execution queue (IEQ) for storing the operation code of each instruction issued by said means for issuing instructions in program order; an input stack associated with each execution unit except the unit which executes the subset of instruction repertoire that is executable within one clock period; a results stack associated with each execution unit for storing the results of the execution of instructions by its associated execution unit in the order executed; a master safe store and a store stack for storing the results in program order of the execution of each instruction executed by the execution units; and collector control means responsive to the order in which instructions are received by the instruction execution queue for causing results stored in the result stacks associated with each execution unit to be stored in program order in the master safe store if the results change the contents of an addressable register and to be stored in the store stack in program order if the results are to be written into memory.

Claim 7

In a central processing unit (CPU) of a synchronous digital data processing system having a memory, said CPU having program addressable registers, a repertoire of instructions, a plurality of execution units, wherein each of said execution unit executes a different subset of the repertoire of instructions independently of and in parallel with the other execution units and each executes the instructions in the order received, at least one of said execution units executing a subset of the instructions that can be executed in one clock period, the number of clock periods required to execute each instruction differing such that the results of the execution of instructions of a give program by the instruction execution units are not produced in program order, said CPU having means for issuing instructions in program order, said means for issuing instructions in program order issuing instructions to the execution unit capable of executing the issued instruction, the improvements comprising: an instruction execution queue (IEQ) for storing the operation code of each instruction issued by said means for issuing instructions in program order; an input stack associated with each execution unit except the unit which executes the subset of instruction repertoire that is executable within one clock period; a results stack associated with each execution unit for storing the results of the execution of instructions by its associated execution unit in the order executed; a master safe store and a store stack for storing the results in program order of the execution of each instruction executed by the execution units; and collector control means responsive to the order in which instructions are received by the instruction execution queue for causing results stored in the result stacks associated with each execution unit to be stored in program order in the master safe store if the results change the contents of an addressable register and to be stored in the store stack in program order if the results are to be written into memory.

Claim 8

In a central processing unit as defined in claim 5 in which the instruction execution queue is a fifo stack.

Claim 9

In a central processing unit as defined in claim 6 in which the input stack associated with an execution unit is a fifo stack.

Claim 10

In a central processing unit as defined in claim 7 in which the result stack of each of the execution units is a fifo stack.

Claim 11

In a central processing unit as defined in claim 8 in which the store stack is a fifo stack.

Claim 12

In a central processing unit as defined in claim 9 in which each of the fifo stacks is a sixteen-level stack.

Claim 13

A collector for a synchronous central processor unit (CPU) having program addressable registers, a memory, a repertoire of instructions, said CPU having a plurality of execution units, wherein each of said execution unit executes a different predetermined set of operation codes of the instruction repertoire independently of and in parallel with the other execution units and each executes the instructions in the order in which instructions are received by each such execution unit, the number of clock periods required to execute each instruction differing such that the results of the execution of instructions of a given program by the instruction execution units are not produced in program order, said CPU having means for issuing in program order instructions to the execution unit capable of executing the operation code of each instruction so issued, and means for issuing in program order instruction execution queue words which include the operation code of each instruction issued to the execution unit; said collector comprising: an instruction execution queue (IEQ) for receiving instruction execution queue words from the means for issuing instruction execution queue words; a plurality of result stacks, one result stack being associated with each execution unit; each execution unit results stack receiving the results of the execution of each operation code by its associate execution unit; a master safe store and a store stack for storing the results in program order of the execution of each instruction executed by the execution units; and collector control means responsive to the order in which instructions are received by the instruction executin queue for causing results stored in the result stacks associated with each execution unit to be stored in program order in the master safe store if the results change the contents of an addressable register and to be stored in the store stack in program order if the results are to be written into memory.

Claim 14

A collector for a synchronous central processor unit (CPU) having program addressable registers, a memory, a repertoire of instructions, said CPU having a plurality of execution units, wherein each of said execution unit executes a different predetermined set of operation codes of the instruction repertoire independently of and in parallel with the other execution units and each executes the instructions in the order in which instructions are received by each such execution unit, the number of clock periods required to execute each instruction differing such that the results of the execution of instructions of a given program by the instruction execution units are not produced in program order, said CPU having means for issuing in program order instructions to the execution unit capable of executing the operation code of each instruction so issued, and means for issuing in program order instruction execution queue words which include the operation code of each instruction issued to the execution unit; said collector comprising: an instruction execution queue (IEQ) for receiving instruction execution queue words from the means for issuing instruction execution queue words; a plurality of result stacks, one result stack being associated with each execution unit; each execution unit results stack receiving the results of the execution of each operation code by its associate execution unit; a master safe store and a store stack for storing the results in program order of the execution of each instruction executed by the execution units; and collector control means responsive to the order in which instructions are received by the instruction executin queue for causing results stored in the result stacks associated with each execution unit to be stored in program order in the master safe store if the results change the contents of an addressable register and to be stored in the store stack in program order if the results are to be written into memory.

Claim 15

A collector for a central processor as defined in claim 11 in which the instruction execution queue is a fifo stack.

Claim 16

A collector for a central processor as defined in claim 12 in which each of the plurality of result stacks is a fifo stack.

Claim 17

A collector for a central processor as defined inn claim 13 in which the control means comprises store processing logic, collector sequence control, and results stack unload control.

Claim 18

A collector for a synchronous central processor unit (CPU) of a data processing system having a system memory, said CPU having a repertoire of instructions, the CPU having a plurality of execution units, each execution unit having program addressable registers, wherein each execution unit executes a different predetermined subset of operation codes of the repertoire of instructions, each instruction requiring a number of clock periods to execute, the minimum number of clock periods to execute an instruction being one, the subset of instructions executed by one of said execution units being limited to those that can be executed in one clock period, The number of clock periods required to execute each instruction differing such that the results of the execution of a given program by the instruction execution units are not produced in program, order, said CPU having means for issuing in program order instructions to the execution unit capable of executing each operation code issued to it, and means for issuing in program order instruction execution queue (IEQ) words which include the operation code of each instruction issued to an execution unit; an input stack associated with each execution unit other than said one unit which executes the subset of instructions which require only one clock period to execute, said input stacks storing instructions issued to its associated execution unit in the order received and holding said instructions until executed, said collector comprising: an instruction execution queue adapted to receive and store IEQ words from the means for issuing IEQ words in the order issued; a plurality of result stacks, one such result stack being associated with each execution unit, each execution unit result stack receiving the results of the execution of operation codes by the execution unit with which it is associated in the order executed; a master safe store for storing changes to the contents of program addressable registers in program order; a store stack for storing the results in program order of the execution of each operation code that changes data to be stored in system memory; and collector control means responsive to the order in which operation codes are received by the instruction execution queue for causing results stored in the result stacks associated with the execution units to be stored in program order in the master safe store if the result changes the contents of a programmable addressable register and in the store stack in program order if the results change the data stored in a memory location in system memory.

Claim 19

A collector for a synchronous central processor unit (CPU) of a data processing system having a system memory, said CPU having a repertoire of instructions, the CPU having a plurality of execution units, each execution unit having program addressable registers, wherein each execution unit executes a different predetermined subset of operation codes of the repertoire of instructions, each instruction requiring a number of clock periods to execute, the minimum number of clock periods to execute an instruction being one, the subset of instructions executed by one of said execution units being limited to those that can be executed in one clock period, The number of clock periods required to execute each instruction differing such that the results of the execution of a given program by the instruction execution units are not produced in program, order, said CPU having means for issuing in program order instructions to the execution unit capable of executing each operation code issued to it, and means for issuing in program order instruction execution queue (IEQ) words which include the operation code of each instruction issued to an execution unit; an input stack associated with each execution unit other than said one unit which executes the subset of instructions which require only one clock period to execute, said input stacks storing instructions issued to its associated execution unit in the order received and holding said instructions until executed, said collector comprising: an instruction execution queue adapted to receive and store IEQ words from the means for issuing IEQ words in the order issued; a plurality of result stacks, one such result stack being associated with each execution unit, each execution unit result stack receiving the results of the execution of operation codes by the execution unit with which it is associated in the order executed; a master safe store for storing changes to the contents of program addressable registers in program order; a store stack for storing the results in program order of the execution of each operation code that changes data to be stored in system memory; and collector control means responsive to the order in which operation codes are received by the instruction execution queue for causing results stored in the result stacks associated with the execution units to be stored in program order in the master safe store if the result changes the contents of a programmable addressable register and in the store stack in program order if the results change the data stored in a memory location in system memory.

Claim 20

A collector as defined in claim 15 in which the instruction execution queue is a fifo stack.

Claim 21

A collector as defined in claim 16 in which each of the result stacks is a fifo stack.

Claim 22

A collector as defined in claim 17 in which the store stack is a fifo stack.

Claim 23

A collector as defined in claim 18 in which the collector control means comprises store processing logic, collector sequence control, and results stack unload control.