Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical polish rate

Claim 1

A method for planarizing a semiconductor topography, comprising the steps of: providing an upper topography of a semiconductor substrate; depositing a first insulating layer upon said upper topography; spin depositing a second insulating layer of adjustable chemical and mechanical properties upon said first insulating layer; heating said second insulating layer to a temperature level and for a time duration necessary to adjust the chemical and mechanical properties such that the second insulating layer is less susceptible to a chemical-mechanical polish than said first insulating layer; and applying a chemical-mechanical polish for removing said second insulating layer at a lesser rate than said first insulating layer in accordance with the chemical and mechanical properties set in the immediately preceding step, wherein said second insulating layer is removed at a lesser rate than said first insulating layer throughout said applying step.

Claim 2

A method for planarizing a semiconductor topography, comprising the steps of: providing an upper topography of a semiconductor substrate; depositing a first insulating layer upon said upper topography; spin depositing a second insulating layer of adjustable chemical and mechanical properties upon said first insulating layer; heating said second insulating layer to a temperature level and for a time duration necessary to adjust the chemical and mechanical properties such that the second insulating layer is less susceptible to a chemical-mechanical polish than said first insulating layer; and applying a chemical-mechanical polish for removing said second insulating layer at a lesser rate than said first insulating layer in accordance with the chemical and mechanical properties set in the immediately preceding step, wherein said second insulating layer is removed at a lesser rate than said first insulating layer throughout said applying step.

Claim 13

A method for planarizing a semiconductor topography, comprising the steps of: inserting into a chamber a semiconductor substrate having an upper surface overlying densely populated areas of less than 2 mm. spacing between elements and sparsely populated areas of greater than 2 mm. spacing between elements; heating said chamber to a level less than 450° C. and, using tetraethoxysilane as the silicon source material, chemical vapor depositing a first insulating layer of silicon dioxide upon said semiconductor substrate; placing said semiconductor substrate upon a rotating wheel and applying a liquid solution of silicate upon said first insulating layer to form a second insulating layer; heating the combination of said semiconductor substrate and said first and second insulating layers to change the chemical and mechanical characteristics of only said second insulating layer, wherein said heat is chosen between 250° C. and 450° C. and for a time duration between 10 min. and 120 min., and wherein increase in temperature and duration will proportionally make less susceptible said second insulating layers to a chemical-mechanical polish; subjecting said second insulating layer first and said first insulating layer second to a chemical-mechanical polish comprising an alkali silica slurry and a polishing pad pressure in the 10 to 20 lbs/in 2 range, wherein said second insulating layer is removed at a slower rate than said first insulating layer and, after portions of said second insulating layer are removed, first insulating layer underlying said portions are removed at a faster rate than remaining portions of said second insulating layer are removed to present an upper surface of partially removed said first and second insulating layers which is more planar in the densely populated areas than the second insulating layer upper surface formed during the placing step; repeating the above steps to present an upper surface comprising partially removed said first and second insulating layers which is more planar in the sparsely populated areas than the second insulating layer upper surface formed during the placing step; and depositing a third insulating layer of silicon dioxide upon the upper surface of partially removed said first and second insulating layers.

Claim 14

A method for planarizing a semiconductor topography, comprising the steps of: inserting into a chamber a semiconductor substrate having an upper surface overlying densely populated areas of less than 2 mm. spacing between elements and sparsely populated areas of greater than 2 mm. spacing between elements; heating said chamber to a level less than 450° C. and, using tetraethoxysilane as the silicon source material, chemical vapor depositing a first insulating layer of silicon dioxide upon said semiconductor substrate; placing said semiconductor substrate upon a rotating wheel and applying a liquid solution of silicate upon said first insulating layer to form a second insulating layer; heating the combination of said semiconductor substrate and said first and second insulating layers to change the chemical and mechanical characteristics of only said second insulating layer, wherein said heat is chosen between 250° C. and 450° C. and for a time duration between 10 min. and 120 min., and wherein increase in temperature and duration will proportionally make less susceptible said second insulating layers to a chemical-mechanical polish; subjecting said second insulating layer first and said first insulating layer second to a chemical-mechanical polish comprising an alkali silica slurry and a polishing pad pressure in the 10 to 20 lbs/in 2 range, wherein said second insulating layer is removed at a slower rate than said first insulating layer and, after portions of said second insulating layer are removed, first insulating layer underlying said portions are removed at a faster rate than remaining portions of said second insulating layer are removed to present an upper surface of partially removed said first and second insulating layers which is more planar in the densely populated areas than the second insulating layer upper surface formed during the placing step; repeating the above steps to present an upper surface comprising partially removed said first and second insulating layers which is more planar in the sparsely populated areas than the second insulating layer upper surface formed during the placing step; and depositing a third insulating layer of silicon dioxide upon the upper surface of partially removed said first and second insulating layers.