US5332694A
Expired / Lapsed
US
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Process for manufacturing a semiconductor device
Assignee: NEC Electronics Corp
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Filing: 1993-02-23
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Granted: 1994-07-26
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Expires: 2013-02-23
Abstract
Abstract A process for manufactoring a semiconductor device having a double- or multi-level interconnection structure is disclosed. The process includes steps of: forming a first level metal interconnect; then forming a first silicon oxide layer by PECVD, and forming a second silicon oxide layer by atmospheric CVD using tetraethoxysilane and oxygen containing ozone under a condition of excess ozone in which the ratio of flow-rate of ozone to flow-rate of tetraethoxysilane is about 20:1. An organic compound coating layer is formed by spin-coating accompanied by a thermal treatment. The organic compound coating layer and the second silicon oxide layer are etched-back to remove the compound oxide layer completely. A third silicon oxide layer is formed by PECVD; and forming a second level metal interconnect. A good planarization can be obtained and a failure, such as delamination or blister due to bumping, of the third silicon oxide layer can be avoided. Hence, a high yield and a high reliability of the semiconductor device having a double- or multi-level interconnection structure can be achieved.
Inventors
- 👤 Mieko Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:03
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
149 words
A process for manufacturing a semiconductor device including steps of: forming a first level interconnect on an insulation layer covering semiconductor active elements fabricated on a substrate; forming a first silicon oxide layer on said first level interconnect and said insulation layer; forming a second silicon oxide layer by atmospheric-pressure CVD on said first silicon oxide layer using tetraethoxysilane (Si(OC 2 H 5 ) 4 ) and oxygen containing ozone, the ratio of the flow-rate of ozone to the flow-rate of tetraethoxysilane being above about 10:1; forming an organic compound coating layer on said second silicon oxide layer by spin-coating; etching-back said organic compound coating layer and said second silicon oxide layer by dry etching to remove the organic compound coating layer; after said etching-back, forming a third silicon oxide layer on said second silicon oxide layer; and forming a second level interconnect on said third silicon oxide layer.
Claim 2
Dependent Claim
149 words
A process for manufacturing a semiconductor device including steps of: forming a first level interconnect on an insulation layer covering semiconductor active elements fabricated on a substrate; forming a first silicon oxide layer on said first level interconnect and said insulation layer; forming a second silicon oxide layer by atmospheric-pressure CVD on said first silicon oxide layer using tetraethoxysilane (Si(OC 2 H 5 ) 4 ) and oxygen containing ozone, the ratio of the flow-rate of ozone to the flow-rate of tetraethoxysilane being above about 10:1; forming an organic compound coating layer on said second silicon oxide layer by spin-coating; etching-back said organic compound coating layer and said second silicon oxide layer by dry etching to remove the organic compound coating layer; after said etching-back, forming a third silicon oxide layer on said second silicon oxide layer; and forming a second level interconnect on said third silicon oxide layer.
Claim 3
Dependent Claim
34 words
A process for manufacturing a semiconductor device as defined in claim 1, wherein said second silicon oxide layer is formed in a thickness of about 1.0 μm to 2.0 μm by said atmospheric-pressure CVD.
Claim 4
Dependent Claim
34 words
A process for manufacturing a semiconductor device as defined in claim 1, wherein said second silicon oxide layer is etched-back at a higher etch rate than said organic compound coating layer during said etching-back.
Claim 5
Dependent Claim
28 words
A process for manufacturing a semiconductor device as defined in claim 1, wherein said organic compound coating layer contains at least one organosilicon compound as a main ingredient.
Claim 6
Dependent Claim
30 words
A process for manufacturing a semiconductor device as defined in claim 1, wherein said organic compound coating layer has an average thickness between about 0.2 μm and about 0.8 μm.
Claim 7
Dependent Claim
73 words
A process for manufacturing a semiconductor device as defined in claim 1, wherein said organic compound coating layer contains as a main gradient at least one member selected from the group consisting of (R 1 ) n --Si(OH) 4-n , Si(OR 2 ) 4 and (R 1 ) n --Si(OR 2 ) 4-n , wherein R1 and R2 are a monovalent hydrocarbon group and an alkyl group, respectively, and n=1, 2 or 3.
Claim 8
Dependent Claim
25 words
A process for manufacturing a semiconductor device as defined in claim 1, wherein said organic compound coating layer contains a photoresist as a main ingredient.
Claim 9
Dependent Claim
34 words
A process for manufacturing a semiconductor device as defined in claim 7, wherein said photoresist is a member selected from the group consisting of novolac resin based resist and polyvinyl phenolic resin based resist.
Claim 10
Dependent Claim
30 words
A process for manufacturing a semiconductor device as defined in claim 7, wherein said organic compound coating layer has an average thickness between about 0.1 μm and about 0.5 μm.
Claim 11
Dependent Claim
35 words
A process for manufacturing a semiconductor device as defined in claim 1, wherein said first silicon oxide layer has a thickness between about 0.03 μm and about 0.5 μm and is formed by plasma-enhanced CVD.
Claim 12
Dependent Claim
35 words
A process for manufacturing a semiconductor device as defined in claim 1, wherein said third silicon oxide layer has a thickness between about 0.2 μm and about 0.5 μm and is formed by plasma-enhanced CVD.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-07-25 | 1998-01-24 | 1998-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-25 | 2002-01-24 | 2002-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-25 | 2006-01-24 | 2006-07-26 | $7700.00 | Window Closed / Lapsed |