US5155064A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fabrication method of a semiconductor device having a planarized surface
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1991-06-10
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Granted: 1992-10-13
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Expires: 2011-06-10
Abstract
Abstract A semiconductor device having a multi-level interconnection structure includes an active device, a substrate supporting the active device thereon, and a first insulator layer provided so as to cover the substrate including the active device. A first conductor pattern is provided on the first insulator layer. A planarizing layer has a planarized top surface provided on the first insulator layer so as to bury the first conductor pattern underneath. A second insulator layer is provided on the planarized top surface of the planarizing layer. A contact hole is provided on the second insulator layer so as to expose a desired part of the first conductor pattern. A second conductor pattern is provided on the second insulator layer in correspondence to the contact hole so as to fill the contact hole and so as to make a contact to the exposed part of the first conductor pattern. An isolated region is provided on the substrate in correspondence to a part of the substrate underneath the contact hole such that the isolated region is projected from the first top surface of the substrate in correspondence to the contact hole. The isolated region causes a projection of the top surface of the first insulator layer in correspondence to a part which covers the isolated region such that the planarizing layer provided on the first insulator layer is eliminated from the part of the first insulator having the projecting top surface.
Inventors
- 👤 Tatsuya Mise
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:57
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; H10P; H10P95/00; H10W20/092; H10W20/40; H10W20/41; H10W20/42
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
195 words
A method for fabricating a semiconductor device having a multi-level interconnection structure, said semiconductor device comprising one or more active devices formed on a surface of a substrate, said method comprising the steps of: providing a first insulator layer on the substrate; providing a patterned first layer interconnection conductor on the first insulator layer; providing an isolated region on the patterned first interconnection conductor such that the isolated region is projected substantially above the first insulator layer in correspondence to where a contact hole is to be provided; providing a planarizing layer on the first insulator layer in a form of a liquid state spin-on-glass by spin-coating, with a thickness such that the isolated region is exposed above the planarizing layer; curing the planarizing layer; providing a second insulator layer on the planarizing layer including the isolated region; providing the contact hole through the second insulator layer and further through the isolated region, such that the first layer interconnection conductor is exposed by the contact hole; and providing a patterned second layer interconnection conductor on the second insulator layer including the contact hole such that the patterned second layer interconnection conductor fills the contact hole.
Claim 2
Independent Claim
195 words
A method for fabricating a semiconductor device having a multi-level interconnection structure, said semiconductor device comprising one or more active devices formed on a surface of a substrate, said method comprising the steps of: providing a first insulator layer on the substrate; providing a patterned first layer interconnection conductor on the first insulator layer; providing an isolated region on the patterned first interconnection conductor such that the isolated region is projected substantially above the first insulator layer in correspondence to where a contact hole is to be provided; providing a planarizing layer on the first insulator layer in a form of a liquid state spin-on-glass by spin-coating, with a thickness such that the isolated region is exposed above the planarizing layer; curing the planarizing layer; providing a second insulator layer on the planarizing layer including the isolated region; providing the contact hole through the second insulator layer and further through the isolated region, such that the first layer interconnection conductor is exposed by the contact hole; and providing a patterned second layer interconnection conductor on the second insulator layer including the contact hole such that the patterned second layer interconnection conductor fills the contact hole.
Claim 3
Dependent Claim
22 words
A method as claimed in claim 1 in which said isolated region comprises silicon oxide deposited by a chemical vapor deposition process.
Claim 4
Dependent Claim
27 words
A method as claimed in claim 1 in which said isolated region is provided on a depressed part of the first insulator layer between the active devices.
Claim 5
Independent Claim
248 words
A method for fabricating a semiconductor device having a multi-level interconnection structure, said semiconductor device comprising an active device formed on a surface of a substrate said method comprising steps of: providing a first insulation layer on the substrate so as to cover the active devices on the substrate; providing an isolated region on the first insulator layer in correspondence to a depressed part of the first insulation layer such that the isolated region is projected to a level at least flush to the first insulator layer in correspondence to where a contact hole is to be provided; providing a second insulation layer on the first insulation layer so as to cover the isolated region provided thereon; providing a patterned first layer interconnection conductor on the second insulator layer such that the first layer interconnection conductor extends at least over the isolated region; providing a planarizing layer on the second insulator layer in a form of a liquid state spin-on-glass by spin-coating, with a thickness such that the planarizing layer is eliminated from a region of the second insulation layer above the isolated region; curing the planarizing layer; providing a third insulator layer on the planarizing layer; providing the contact hole through the third insulator layer such that the first layer interconnection conductor is exposed by the contact hole; and providing a patterned second layer interconnection conductor on the second insulator layer including the contact hole such that the patterned second layer interconnection conductor fills the contact hole.
Claim 6
Independent Claim
248 words
A method for fabricating a semiconductor device having a multi-level interconnection structure, said semiconductor device comprising an active device formed on a surface of a substrate said method comprising steps of: providing a first insulation layer on the substrate so as to cover the active devices on the substrate; providing an isolated region on the first insulator layer in correspondence to a depressed part of the first insulation layer such that the isolated region is projected to a level at least flush to the first insulator layer in correspondence to where a contact hole is to be provided; providing a second insulation layer on the first insulation layer so as to cover the isolated region provided thereon; providing a patterned first layer interconnection conductor on the second insulator layer such that the first layer interconnection conductor extends at least over the isolated region; providing a planarizing layer on the second insulator layer in a form of a liquid state spin-on-glass by spin-coating, with a thickness such that the planarizing layer is eliminated from a region of the second insulation layer above the isolated region; curing the planarizing layer; providing a third insulator layer on the planarizing layer; providing the contact hole through the third insulator layer such that the first layer interconnection conductor is exposed by the contact hole; and providing a patterned second layer interconnection conductor on the second insulator layer including the contact hole such that the patterned second layer interconnection conductor fills the contact hole.
Claim 7
Dependent Claim
54 words
A method as claimed in claim 3 in which said method further comprises a step of providing a polysilicon interconnection at a level above the first insulator layer and below the second insulator layer, said isolated region comprises polysilicon, and said isolated region is provided simultaneously to the step of providing the polysilicon interconnection.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-13 | 1996-04-13 | 1996-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-13 | 2000-04-13 | 2000-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-13 | 2004-04-13 | 2004-10-13 | $7700.00 | Window Closed / Lapsed |