US5169801A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating a semiconductor device
Assignee: Micron Memory Japan Ltd
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Filing: 1991-12-31
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Granted: 1992-12-08
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Expires: 2011-12-31
Abstract
Abstract A method for fabricating a semiconductor device comprises the steps of forming an insulating layer by the CVD method on a main surface of a semiconductor substrate, fluidizing the insulating layer by heat treatment, unifying a thickness of the insulating layer, opening contact holes in desired points of the insulating layer, and forming conductor contacts for interconnection on the contact holes. The insulating layer is has a uniform thickness in any area on the semiconductor device, so that over-etching of the insulating layer in opening contact holes can be prevented, and the step coverage is well improved.
Inventors
- 👤 Natsuki Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:10
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10P; H10P95/00; H10W20/081; Y; Y10; Y10S; Y10S148/00; Y10S148/133; Y10S438/00; Y10S438/978
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
206 words
A method for fabricating a semiconductor device, comprising the steps of: forming a first insulating layer having a reflow property by CVD on a main surface of a semiconductor substrate, said first insulating layer being a material which is fluidized by a heat treatment, and having a uniform thickness on a predetermined area thereof; fluidizing the first insulating layer by a heat treatment; coating the first insulating layer with a spin coat layer; etching-back at least the spin coat layer by RIE; forming a second insulating layer having a reflow property by CVD on said first insulating layer, said second insulating layer being a material which is fluidized by a heat treatment, and having a uniform thickness on a predetermined area thereof; fluidizing the first and second insulating layers by a heat treatment; opening a contact hole passing through said first and second insulating layers at a predetermined position thereon; fluidizing said first and second insulating layers having said contact hole for rounding an upper edge of the contact hole by a heat treatment; and providing a conductor contact for interconnection in said contact hole with a lower portion, a sidewall of the contact hole being of continuous layers, all of which have a reflow property.
Claim 2
Independent Claim
206 words
A method for fabricating a semiconductor device, comprising the steps of: forming a first insulating layer having a reflow property by CVD on a main surface of a semiconductor substrate, said first insulating layer being a material which is fluidized by a heat treatment, and having a uniform thickness on a predetermined area thereof; fluidizing the first insulating layer by a heat treatment; coating the first insulating layer with a spin coat layer; etching-back at least the spin coat layer by RIE; forming a second insulating layer having a reflow property by CVD on said first insulating layer, said second insulating layer being a material which is fluidized by a heat treatment, and having a uniform thickness on a predetermined area thereof; fluidizing the first and second insulating layers by a heat treatment; opening a contact hole passing through said first and second insulating layers at a predetermined position thereon; fluidizing said first and second insulating layers having said contact hole for rounding an upper edge of the contact hole by a heat treatment; and providing a conductor contact for interconnection in said contact hole with a lower portion, a sidewall of the contact hole being of continuous layers, all of which have a reflow property.
Claim 3
Dependent Claim
46 words
A method for fabricating a semiconductor device, according to claim 1: wherein the thickness of said spin coat layer is adjusted so that the thickness of the layer which consists of said spin coat layer and said first insulating layer is unified on said semiconductor device.
Claim 4
Dependent Claim
24 words
A method for fabricating a semiconductor device, according to claim 1: wherein said first and second insulating layers are made of the same material.
Claim 5
Dependent Claim
24 words
A method for fabricating a semiconductor device, according to claim 1: wherein said first and second insulating layers are made of the different materials.
Claim 6
Dependent Claim
28 words
A method for fabricating a semiconductor device, according to claim 1: wherein at least one of said first and second insulating layer is made of phosphosilicate glass (PSG).
Claim 7
Dependent Claim
28 words
A method for fabricating a semiconductor device, according to claim 1: wherein at least one of said first and second insulating layer is made of borophosphosilicate glass (BPSG).
Claim 8
Dependent Claim
22 words
A method for fabricating a semiconductor device, according to claim 1: wherein said spin coat layer is made of a silica film.
Claim 9
Dependent Claim
22 words
A method for fabricating a semiconductor device, according to claim 1: wherein said spin coat layer is made of an organic material.
Claim 10
Independent Claim
133 words
A method for fabricating a semiconductor device, comprising the steps of: forming a first insulating layer of glass on a step portion of a main surface of a semiconductor substrate; fluidizing said first insulating layer by a heat treatment; forming a spin coat insulating layer on said fluidized first insulating layer; etching-back at least said spin coat insulating layer by a reactive ion etching method; forming a second insulation layer of glass on said first insulating layer; fluidizing said first and second insulating layers by a heat treatment; opening a contact hole at a predetermined position on said first and second insulating layers; fluidizing by heat treating said first and second insulating layers containing said contact hole; and providing a conductor contact for interconnection through said contact hole with a lower portion thereof.
Claim 11
Independent Claim
133 words
A method for fabricating a semiconductor device, comprising the steps of: forming a first insulating layer of glass on a step portion of a main surface of a semiconductor substrate; fluidizing said first insulating layer by a heat treatment; forming a spin coat insulating layer on said fluidized first insulating layer; etching-back at least said spin coat insulating layer by a reactive ion etching method; forming a second insulation layer of glass on said first insulating layer; fluidizing said first and second insulating layers by a heat treatment; opening a contact hole at a predetermined position on said first and second insulating layers; fluidizing by heat treating said first and second insulating layers containing said contact hole; and providing a conductor contact for interconnection through said contact hole with a lower portion thereof.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-08 | 1996-06-08 | 1996-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-08 | 2000-06-08 | 2000-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-08 | 2004-06-08 | 2004-12-08 | $7700.00 | Window Closed / Lapsed |