US5143860A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High density EPROM fabricaiton method having sidewall floating gates
Assignee: Texas Instruments Inc
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Filing: 1991-04-17
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Granted: 1992-09-01
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Expires: 2011-04-17
Abstract
Abstract An EPROM memory having sidewall floating gates (30) is disclosed. Sidewall floating gates (30) are formed on sidewalls (28) of field insulators (24). Spaced apart bit lines (22), which serve as memory cell sources and drains, are formed. The field insulators (24) overlie the bit lines (22), and sidewall floating gates are formed on the sidewalls (28) of the field insulators (24). In one embodiment, a second set of bit lines (36) is formed between the sidewall floating gates (30), and each memory cell contains one sidewall floating gate (30). In another embodiment, each memory cell contains two sidewall floating gate (30), and the memory cell may be programmed to store from two to four distinct information states.
Inventors
- 👤 Allan T. Mitchell
- 👤 Bert R. Riemenschneider
- 👤 Howard L. Tigilaar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:41
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5642; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/0458; G11C16/0466; G11C16/0475; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/687; H10D30/6891; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/0133; H10D64/031; H10D64/035; G11C2211/00; G11C2211/56; G11C2211/561; G11C2211/5612
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
184 words
A method of forming an electrically programmable memory on a substrate having a semiconductor surface area of a first conductivity type, said method comprising the steps of: forming first and second spaced apart regions of a second conductivity type at the semiconductor surface, said first and second regions of said second conductivity type spaced apart by a first region of said first conductivity type at the semiconductor surface, said first region of said first conductivity type extending from said first region of said second conductivity type to said second region of said second conductivity type; forming first and second field insulator regions overlying the first and second regions of said second conductivity type, respectively, so that said first and second field insulator regions have first and second sidewalls, respectively, the first sidewall facing the second sidewall and the first and second sidewalls extending away from the substrate surface; and forming first and second sidewall floating gates on the first and second sidewalls, respectively, said first and second sidewall floating gates spaced apart by a portion of said first region of said first conductivity type.
Claim 2
Independent Claim
184 words
A method of forming an electrically programmable memory on a substrate having a semiconductor surface area of a first conductivity type, said method comprising the steps of: forming first and second spaced apart regions of a second conductivity type at the semiconductor surface, said first and second regions of said second conductivity type spaced apart by a first region of said first conductivity type at the semiconductor surface, said first region of said first conductivity type extending from said first region of said second conductivity type to said second region of said second conductivity type; forming first and second field insulator regions overlying the first and second regions of said second conductivity type, respectively, so that said first and second field insulator regions have first and second sidewalls, respectively, the first sidewall facing the second sidewall and the first and second sidewalls extending away from the substrate surface; and forming first and second sidewall floating gates on the first and second sidewalls, respectively, said first and second sidewall floating gates spaced apart by a portion of said first region of said first conductivity type.
Claim 3
Dependent Claim
34 words
A method as claimed in claim 1 additionally comprising the step of forming a control gate overlying a surface of the first sidewall floating gate and a surface of the second sidewall floating gate.
Claim 4
Dependent Claim
68 words
A method as claimed in claim 2 wherein said step of forming a control gate comprises the steps of: forming a gate insulator on the semiconductor surface between the first and second regions of said second conductivity type; and extending the control gate toward the semiconductor surface between said first and second regions of said second conductivity type so that the control gate resides on the gate insulator.
Claim 5
Dependent Claim
32 words
A method as claimed in claim 1 wherein said forming field insulator regions step comprises the step of forming the first and second sidewalls to be substantially perpendicular to the semiconductor surface.
Claim 6
Dependent Claim
65 words
A method as claimed in claim 1 additionally comprising the step of forming a third region of the second conductivity type at the semiconductor surface, the third region of said second conductivity type being spaced apart form the first and second regions of said second conductivity type, and the third region of said second conductivity type residing between said first and second sidewall floating gates.
Claim 7
Dependent Claim
74 words
A method as claimed in claim 5 additionally comprising the steps of: forming a third field insulator region overlying the third region of said second conductivity type; forming a first interlevel insulator on a surface of the first sidewall floating gate; forming a second interlevel insulator on a surface of the second sidewall floating gate; and forming a control gate overlying the third field insulator, the first interlevel insulator, and the second interlevel insulator.
Claim 8
Dependent Claim
29 words
A method as claimed in claim 5 wherein said forming a third region of the second conductivity type comprises the step of implanting dopant ions into the semiconductor surface.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-01 | 1996-03-02 | 1996-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-01 | 2000-03-02 | 2000-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-01 | 2004-03-02 | 2004-09-01 | $7700.00 | Window Closed / Lapsed |