Multiplexing sense amplifier

Claim 2

A memory system comprising: a memory array having at least first and second pairs of data lines corresponding to columns in the memory array; and a multiplexing sense amplifier including a selection stage having input lines connected to the first and second pairs of data lines, the selection stage also having a true output line and a complement output line, wherein output signals generated in the output lines are controlled by a first and second set of transistors, wherein each transistor in the first set has a gate connected to one of the input lines and each transistor in the second set is connected in series with one of the transistors in the first set and may be selectively turned on and turned off, wherein one of the two pairs of data lines may be selected by turning transistors on and off in the second set, wherein said multiplexing sense amplifier includes a common current source provided by a control transistor having a first source/drain connected to a power supply voltage and a second source/drain connected to the first and second sets of transistors by a common node, wherein the multiplexing sense amplifier may be enabled and disabled by turning the control transistor on and off, and wherein the selection stage further includes a p-channel cross-coupled amplifier.

Claim 3

The memory system of claim 1 further comprising an amplifying stage for generating logic output signals in response to the output signals from the selection stage.

Claim 4

The memory system of claim 2, wherein the amplifying stage comprises a flip-flop.

Claim 5

The memory system of claim 2, wherein the amplifying stage comprises a p-channel cross-coupled metal-oxide semiconductor field effect transistor amplifier.

Claim 6

The memory system of claim 1, wherein the selection stage further comprises two current mirrors.

Claim 7

The memory system of claim 1, wherein the selection stage further comprises a differential amplifier.

Claim 8

The memory system of claim 1, wherein the selection stage further comprises a level shifter circuit.

Claim 9

A multiplexing sense amplifier circuit comprising: a selection stage having inputs connected to first and second data lines, the selection stage also having a true output line and a complement output line, wherein output signals sent to the output lines are controlled by a first and second set of transistors, each transistor in the first set has a gate connected to one of the input lines and each transistor in the second set is connected in series with one of the transistors in the first set and may be selectively turned on and turned off, wherein one of the two data lines may be selected by turning transistors on and off in the second set, wherein said multiplexing sense amplifier includes a common current source provided by a control transistor having a first source/drain connected to a power supply voltage and a second source/drain connected to the first and second sets of transistors by a common node, wherein the multiplexing sense amplifier may be enabled and disabled by turning the control transistor on and off, and further including a p-channel cross-coupled amplifier; and an amplifying stage for generating logic output signals in response to the output signals from the selection stage; wherein each data line is a pair of data lines, and wherein selection of signals from the first data lines may be accomplished by turning on the transistors in the second set of transistors that are connected in series with transistors having gates connected to the first data lines and turning off the transistors in the second set of transistors that are connected in series with transistors having gates connected to the second data lines.

Claim 10

A multiplexing sense amplifier circuit comprising: a selection stage having inputs connected to first and second data lines, the selection stage also having a true output line and a complement output line, wherein output signals sent to the output lines are controlled by a first and second set of transistors, each transistor in the first set has a gate connected to one of the input lines and each transistor in the second set is connected in series with one of the transistors in the first set and may be selectively turned on and turned off, wherein one of the two data lines may be selected by turning transistors on and off in the second set, wherein said multiplexing sense amplifier includes a common current source provided by a control transistor having a first source/drain connected to a power supply voltage and a second source/drain connected to the first and second sets of transistors by a common node, wherein the multiplexing sense amplifier may be enabled and disabled by turning the control transistor on and off, and further including a p-channel cross-coupled amplifier; and an amplifying stage for generating logic output signals in response to the output signals from the selection stage; wherein each data line is a pair of data lines, and wherein selection of signals from the first data lines may be accomplished by turning on the transistors in the second set of transistors that are connected in series with transistors having gates connected to the first data lines and turning off the transistors in the second set of transistors that are connected in series with transistors having gates connected to the second data lines.

Claim 11

The multiplexing sense amplifier of claim 8, wherein the amplifying stage comprises a flip-flop.

Claim 12

The multiplexing sense amplifier of claim 8, wherein the selection stage further comprises two current mirrors.

Claim 13

The multiplexing sense amplifier of claim 8, wherein the selection stage further comprises a differential amplifier.

Claim 14

The multiplexing sense amplifier of claim 8, wherein the selection stage further comprises a level shifter circuit.

Claim 15

The multiplexing sense amplifier of claim 8, wherein the selection stage further comprises one current mirror.