US4907201A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS transistor circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1988-07-14
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Granted: 1990-03-06
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Expires: 2008-07-14
Abstract
Abstract In a MOS transistor circuit (comprising a pair of current mirror circuits, each comprising: first and second MOS transistors having their gate electrodes connected together third and fourth MOS transistors respectively connected in series with the first and second transistors, the third and the fourth MOS transistors of the pair of current mirror circuits receiving a pair of complementary signals at their gate electrodes; and the nodes between the second and the fourth MOS transistors forming output nodes of the current mirror circuit), a pair of capacitors each coupling the output of one current mirror circuit to the gate electrodes of the first and the second MOS transistors of the other current mirror circuit. This provides positive feedback. The change in the outputs responsive to change in the inputs is thereby accelerated.
Inventors
- 👤 Hiroshi Minami
- 👤 Koreaki Fujita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:39
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F2203/00; H03F2203/45; H03F2203/45364; H03F2203/45394; H03F2203/45674; H03F2203/45712
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
234 words
A semiconductor memory device, comprising: a plurality of memory cells, each of which delivers a complementary pair of bitline signals when accessed; and at least one sense amplifier connected to receive said bitline signals from an accessed one of said cells; wherein said sense amplifier comprises first and second voltage amplifiers, each including: first and second active loads; first and second drive transistors, connected to pull current through said first and second active loads respectively; said first drive transistor and active load being connected at a first node, which is also connected to regulate the impedance of said first and second active loads, and said second drive transistor and active load being connected at a second node, which is also connected to provide an output signal of said voltage amplifier; said first drive transistor of said first voltage amplifier and said second drive transistor of said second voltage amplifier being connected to receive one of said bitline signals, and said first drive transistor of said second voltage amplifier and said second drive transistor of said first voltage amplifier being connected to receive the other one of said bitline signals; said second node of said first voltage amplifier also being coupled to partially drive said first node of said second voltage amplifier, and said second node of said second voltage amplifier also being coupled to partially drive said first node of said first voltage amplifier.
Claim 2
Dependent Claim
234 words
A semiconductor memory device, comprising: a plurality of memory cells, each of which delivers a complementary pair of bitline signals when accessed; and at least one sense amplifier connected to receive said bitline signals from an accessed one of said cells; wherein said sense amplifier comprises first and second voltage amplifiers, each including: first and second active loads; first and second drive transistors, connected to pull current through said first and second active loads respectively; said first drive transistor and active load being connected at a first node, which is also connected to regulate the impedance of said first and second active loads, and said second drive transistor and active load being connected at a second node, which is also connected to provide an output signal of said voltage amplifier; said first drive transistor of said first voltage amplifier and said second drive transistor of said second voltage amplifier being connected to receive one of said bitline signals, and said first drive transistor of said second voltage amplifier and said second drive transistor of said first voltage amplifier being connected to receive the other one of said bitline signals; said second node of said first voltage amplifier also being coupled to partially drive said first node of said second voltage amplifier, and said second node of said second voltage amplifier also being coupled to partially drive said first node of said first voltage amplifier.
Claim 3
Dependent Claim
15 words
A device as claimed in claim 1, wherein said drive transistors are field effect transistors.
Claim 4
Dependent Claim
15 words
A device as claimed in claim 1, wherein said active loads are field effect transistors.
Claim 5
Dependent Claim
19 words
A device as claimed in claim 1 wherein said active loads and said drive transistors are field effect transistors.
Claim 6
Dependent Claim
21 words
A device as claimed in claim 1 wherein said active loads are P-MOS transistors and said drive transistors are N-MOS transistors.
References Cited (Backward Citations)
US4825418A
Cited
US4767942A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-05 | 1993-09-04 | 1994-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-05 | 1997-09-04 | 1998-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-05 | 2001-09-04 | 2002-03-06 | $7700.00 | Window Closed / Lapsed |