Integrated memory comprising a sense amplifier

Claim 1

An integrated field-effect transistor memory comprising a plurality of sense amplifiers, each including a parallel connection of a first and a second current branch, each current branch comprising a channel of a control transistor and a channel of a load transistor, said channels in each branch being coupled at respective junction points, the junction point in each current branch being coupled to a gate of the load transistor in the other current branch, at least one of said junction points comprising a sense amplifier output, wherein said control and load transistors are of the same conductivity type, the control transistors are connected in a source-follower configuration, each load transistor is connected to a source of the control transistor in its current branch, and said plurality of sense amplifiers are coupled to one common pair of load transistors, the load transistors being coupled between a data bus and a first supply terminal, and a selection circuit for the selective activation of a single sense amplifier.