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US4811297A
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Boundary-free semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1987-12-14
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Granted: 1989-03-07
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Expires: 2007-12-14
Abstract
Abstract An entire chip is divided into N blocks (N=n×m) in accordance with a desired rectangular group of bits (n×m bits). The same row decoder is provided for every m blocks, and a row address A R or a row address A R+1 adjacent thereto is given to the row decoders. Similarly, the same column decoder is provided for every m blocks, and a column address A C or a column address A C +1 adjacent thereto is given to the column decoders. N bits of memory cells are accessed from the blocks, and the accessed memory cells are rearranged, thereby obtaining a desired rectangular group of bits.
Inventors
- 👤 Junji Ogawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:33
CPC Classifications
G; G11; G11C; G11C7/00; G11C8/00; G11C8/12; G06; G06F; G06F12/00; G06F12/02; G06F12/0207
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
149 words
A semiconductor memory device comprising: n rows×m columns of memory cell blocks; row selecting means provided for each row of said memory cell blocks respectively; m column selecting means provided for each column of said memory cell blocks respectively; a first switching means, connected to said row selecting means, for supplying a row address or a row address adjacent to said row address to each of said row selecting means; a second switching means, connected to said column selecting means, for supplying a column address or a column address adjacent to said column address to each of said column selecting means; and arranging means, connected to said memory cell blocks, for rearranging n rows×m columns of cells of said memory cell blocks selected by said row selecting means and said column selecting means, thereby accessing a voluntary group of n rows×m columns of bits in a random access mode.
Claim 2
Dependent Claim
149 words
A semiconductor memory device comprising: n rows×m columns of memory cell blocks; row selecting means provided for each row of said memory cell blocks respectively; m column selecting means provided for each column of said memory cell blocks respectively; a first switching means, connected to said row selecting means, for supplying a row address or a row address adjacent to said row address to each of said row selecting means; a second switching means, connected to said column selecting means, for supplying a column address or a column address adjacent to said column address to each of said column selecting means; and arranging means, connected to said memory cell blocks, for rearranging n rows×m columns of cells of said memory cell blocks selected by said row selecting means and said column selecting means, thereby accessing a voluntary group of n rows×m columns of bits in a random access mode.
Claim 3
Dependent Claim
36 words
A device as set forth in claim 1, wherein said first and second switching means comprises means for accessing a pointing bit at a special point in said voluntary group of n rows×m columns of bits.
Claim 4
Dependent Claim
21 words
A device as set forth in claim 2, wherein said pointing bit accessing means comprises means for changing said special point.
Claim 5
Dependent Claim
36 words
A device as set forth in claim 3, wherein a part of outputs of said arranging means are in a high impedance state, thereby accessing a voluntary group of n' rows×m' column of bits (n'≦n, m'≦m).
Claim 6
Dependent Claim
92 words
A device as set forth in claim 3, further comprising: n rows×m columns of serial transfer means, each provided in parallel with the row direction of one of said memory cell blocks; a batch transfer means, connected to said serial transfer means and to said memory cell blocks, for carrying out a batch transfer therebetween; and another arranging means, connected to said serial transfer means, for rearranging n rows of said serial transfer for n serial input/output terminal, thereby accessing a voluntary group of n-rows of bits in a serial access mode.
Claim 7
Dependent Claim
34 words
A device as set forth in claim 5, wherein a part of outputs of said another arranging means are in a high impedance state, thereby accessing a voluntary group of n'-rows (n'≦n) of bits.
Claim 8
Dependent Claim
39 words
A device as set forth in claim 5, wherein each of said serial transfer means comprises a shift register said device further comprising n multiplexers, each connected between one row of said shift register and said another arranging means.
Claim 9
Dependent Claim
130 words
A semiconductor memory device comprising: n-rows of memory cell blocks; serial transfer means each provided in parallel with the row direction of one of said memory cell blocks; row selecting means provided commonly for each row of said memory cell blocks respectively; a switching means, connected to said row selecting means, for supplying a row address or a row address adjacent to said row address to each of said row selecting means; a batch transfer means, connected to said serial transfer means and to said memory cell blocks, for carrying out a batch transfer therebetween; an arranging means, connected to said serial transfer means, for rearranging n rows of said serial transfer for n serial input/output terminals, thereby accessing a voluntary group of n-rows bits in a serial access mode.
Claim 10
Dependent Claim
130 words
A semiconductor memory device comprising: n-rows of memory cell blocks; serial transfer means each provided in parallel with the row direction of one of said memory cell blocks; row selecting means provided commonly for each row of said memory cell blocks respectively; a switching means, connected to said row selecting means, for supplying a row address or a row address adjacent to said row address to each of said row selecting means; a batch transfer means, connected to said serial transfer means and to said memory cell blocks, for carrying out a batch transfer therebetween; an arranging means, connected to said serial transfer means, for rearranging n rows of said serial transfer for n serial input/output terminals, thereby accessing a voluntary group of n-rows bits in a serial access mode.
Claim 11
Dependent Claim
39 words
A device as set forth in claim 8, wherein a part of outputs (SIO 0 to SIO n-1 ) of said arranging means are in a high impedance state, thereby accessing a voluntary group Of n'-rows (n'≦n) of bits.
Claim 12
Dependent Claim
37 words
A device as set forth in claim 8, wherein each of said serial transfer means comprises a shift register said device further comprising multiplexers, each connected between one row of said shift register and said arranging means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-06 | 1992-09-05 | 1993-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-06 | 1996-09-05 | 1997-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-06 | 2000-09-05 | 2001-03-07 | $7700.00 | Window Closed / Lapsed |