Floating gate injection voltage regulator

Claim 2

A circuit for regulating floating gate injection voltage, comprising: a floating gate device comprising an electrically conductive floating gate capacitively coupled to a programming terminal by an injection capacitance and to a bias terminal by a bias capacitance; and a voltage regulator electrically coupled to said floating gate device, wherein said voltage regulator establishes a substantially constant rate of charge onto said floating gate when a programming voltage is applied across said floating gate device and said voltage regulator.

Claim 3

The circuit of claim 1 further comprising a voltage source for applying a voltage to said floating gate device and said voltage regulator.

Claim 4

The circuit of claim 1 wherein said voltage regulator comprises a field effect transistor having a gate electrically contiguous with said floating gate, a drain electrically coupled to said bias terminal, and a source electrically coupled to a programming voltage return.

Claim 5

The circuit of claim 3, further comprising a current source electrically coupled to said drain for supplying a bias current to said drain.

Claim 6

The circuit of claim 4, wherein said current source comprises an electrical resistance electrically coupled between said programming terminal and said drain.

Claim 7

The circuit of claim 1, wherein said injection capacitance comprises positive and negative charge injection capacitors, wherein positive charge is transferred from said programming terminal through said positive injection capacitor to said floating gate when said programming voltage applied to said programming terminal is positive, and wherein negative charge is transferred from said programming terminal through said negative injection capacitor to said floating gate when said programming voltage applied to said programming terminal is negative.

Claim 8

The circuit of claim 1, wherein said voltage regulator an n-channel field effect transistor having a gate electrically contiguous with said floating gate, a drain electrically coupled to said bias terminal, and a source electrically coupled in series with a first diode electrically coupled in series with a programming voltage return terminal; said first diode having a polarity to block current flow through said n-channel field effect transistor when said programming voltage applied to said programming terminal is negative; a p-channel field effect transistor having a gate electrically contiguous with said floating gate, a drain electrically coupled to said bias terminal, and a source electrically coupled in series with a second diode electrically coupled in series with said programming voltage return terminal; said second diode having a polarity to block current flow through said p-channel field effect transistor when said programming voltage applied to said programming terminal is positive.

Claim 9

The circuit of claim 7, further comprising a current source electrically coupled to said bias terminal for supplying a positive bias current to said drain of said n-channel field effect transistor when said programming voltage is positive, and a negative bias current to said drain of said p-channel field effect transistor when said programming voltage is negative.

Claim 10

The circuit of claim 8, wherein said current source comprises an electrical resistance electrically coupled between said programming terminal and said bias terminal.

Claim 11

A circuit for regulating floating gate injection voltage, comprising: a floating gate device comprising an electrically conductive floating gate capacitively coupled to a programming terminal by an injection capacitance and to a bias terminal by a bias capacitance; and an injection voltage regulating transistor having a gate electrically contiguous with said floating gate device, a drain electrically coupled to said bias terminal, and a source electrically coupled to a programming voltage return terminal; wherein said injection voltage regulating transistor establishes a substantially constant rate of charge onto said floating gate when a programming voltage is applied across said programming terminal and said programming voltage return terminal.

Claim 12

A circuit for regulating floating gate injection voltage, comprising: a floating gate device comprising an electrically conductive floating gate capacitively coupled to a programming terminal by an injection capacitance and to a bias terminal by a bias capacitance; and an injection voltage regulating transistor having a gate electrically contiguous with said floating gate device, a drain electrically coupled to said bias terminal, and a source electrically coupled to a programming voltage return terminal; wherein said injection voltage regulating transistor establishes a substantially constant rate of charge onto said floating gate when a programming voltage is applied across said programming terminal and said programming voltage return terminal.

Claim 13

The circuit of claim 10 further comprising a voltage source for applying a voltage across said programming terminal and said programming voltage return terminal.

Claim 14

The circuit of claim 10 wherein said injection capacitance comprises positive and negative charge injection capacitors, wherein positive charge is transferred from said programming terminal through said positive injection capacitor to said floating gate when said programming voltage applied to said programming terminal is positive, and wherein negative charge is transferred from said programming terminal through said negative injection capacitor to said floating gate when said programming voltage applied to said programming terminal is negative.

Claim 15

The circuit of claim 12 wherein said injection voltage regulating transistor comprises: an n-channel field effect transistor having a gate electrically contiguous with said floating gate, a drain electrically coupled to said bias terminal, and a source electrically coupled in series with a first diode electrically coupled in series with a programming voltage return terminal; said first diode having a polarity to block current flow through said n-channel field effect transistor when said programming voltage applied to said programming terminal is negative; a p-channel field effect transistor having a gate electrically contiguous with said floating gate, a drain electrically coupled to said bias terminal, and a source electrically coupled in series with a second diode electrically coupled in series with said programming voltage return terminal; said second diode having a polarity to block current flow through said p-channel field effect transistor when said programming voltage applied to said programming terminal is positive.

Claim 16

The circuit of claim 10 further comprising a current source electrically coupled to said bias terminal for supplying a bias current to said n-channel field effect transistor and to said p-channel field effect transistor.

Claim 17

The circuit of claim 14 wherein said current source comprises an electrical resistance electrically coupled between said programming terminal and said bias terminal.