US4888738A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current-regulated, voltage-regulated erase circuit for EEPROM memory
Assignee: Atmel Corp
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Filing: 1988-06-29
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Granted: 1989-12-19
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Expires: 2008-06-29
Abstract
Abstract A control circuit for erasing EEPROM memory cells is disclosed, including a charge pump having two switched constant current sources driven by opposing clocks. Current produced by the current sources is coupled to a node from where it is used to erase EEPROM memory cells. A switch is provided to isolate the device being erased by floating its source.
Inventors
- 👤 Ting-Wah Wong
- 👤 Raul-Adrian Cernea
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:33
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
143 words
A memory circuit including a plurality of EEPROM transistors, each of said transistors including a source and a drain, and an erase circuit, said erase circuit including: first and second constant current sources, means for alternately activating said first and second current sources, first current coupling means for coupling currents from said first and second constant current sources to first and second nodes, respectively, second current coupling means for combining said currents into an erasing current at a third node, means for selecting one of said EEPROM transistors to be erased, means for coupling said erasing current to the drain of said selected EEPROM transistor, means for sensing the voltage at the drain of said selected EEPROM transistor and for deactivating said means for coupling said erasing current when the voltage at the drain of said selected EEPROM transistor reaches a predetermined value.
Claim 2
Dependent Claim
143 words
A memory circuit including a plurality of EEPROM transistors, each of said transistors including a source and a drain, and an erase circuit, said erase circuit including: first and second constant current sources, means for alternately activating said first and second current sources, first current coupling means for coupling currents from said first and second constant current sources to first and second nodes, respectively, second current coupling means for combining said currents into an erasing current at a third node, means for selecting one of said EEPROM transistors to be erased, means for coupling said erasing current to the drain of said selected EEPROM transistor, means for sensing the voltage at the drain of said selected EEPROM transistor and for deactivating said means for coupling said erasing current when the voltage at the drain of said selected EEPROM transistor reaches a predetermined value.
Claim 3
Dependent Claim
15 words
The circuit of claim 1 wherein said first current coupling means are MOS gate capacitors.
Claim 4
Dependent Claim
16 words
The circuit of claim 1 wherein said sensing means is a voltage clamp connected MOS transistor.
Claim 5
Dependent Claim
15 words
The circuit of claim 1 wherein said second current coupling means are diode-connected MOS transistors.
Claim 6
Dependent Claim
20 words
The circuit of claim 1, further including means for floating the source of a selected EEPROM transistor to be erased.
Claim 7
Dependent Claim
28 words
The circuit of claim 5, wherein said means for floating includes a transistor device connected between the source of said selected EEPROM memory transistor and a voltage supply.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-18 | 1993-06-19 | 1993-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-18 | 1997-06-19 | 1997-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-18 | 2001-06-19 | 2001-12-19 | $7700.00 | Window Closed / Lapsed |