Self-limiting erase scheme for EEPROM

Claim 1

An apparatus for self-limiting an electrical erase of a floating gate electrically programmable and electrically erasable read-only memory (EEPROM) cell having first and second doped regions separated by a channel region, and having a floating gate and a control gate overlying said channel region and a portion of said first doped region, comprising: voltage supply means coupled to said first doped region to provide an erase voltage for discharging electrons from said floating gate to said first doped region; feedback means coupled to said second region for providing a feedback signal to limit said discharging; wherein as said floating gate discharges electrons to said first doped region, said second doped region increases in potential and said feedback means uses said potential to provide said feedback signal such that an erasing cycle is terminated prior to over-erasing said EEPROM cell.

Claim 2

An apparatus for self-limiting an electrical erase of a floating gate electrically programmable and electrically erasable read-only memory (EEPROM) cell having first and second doped regions separated by a channel region, and having a floating gate and a control gate overlying said channel region and a portion of said first doped region, comprising: voltage supply means coupled to said first doped region to provide an erase voltage for discharging electrons from said floating gate to said first doped region; feedback means coupled to said second region for providing a feedback signal to limit said discharging; wherein as said floating gate discharges electrons to said first doped region, said second doped region increases in potential and said feedback means uses said potential to provide said feedback signal such that an erasing cycle is terminated prior to over-erasing said EEPROM cell.

Claim 13

A method for self-limiting an electrical erase of an electrically programmable and electrically erasable read-only memory (EEPROM) cell having a source, drain, floating gate and control gate, wherein said source and drain are separated by a channel region, and said floating gate and control gate overlying sad channel region and a portion of said source region, comprising the steps of: providing an erasing potential on said source to cause electrons to tunnel from said floating gate to said source; coupling a potential of said drain as feedback to said control gate, such that as said floating gate is discharged of said electrons, said drain potential increases proportionately to said discharge and said feedbback also causes a proportionate increase in potential at said control gate to counteract said erasing potential; wherein electron discharge is inhibited to prevent over-erasing of said EEPROM cell.

Claim 14

A method for self-limiting an electrical erase of an electrically programmable and electrically erasable read-only memory (EEPROM) cell having a source, drain, floating gate and control gate, wherein said source and drain are separated by a channel region, and said floating gate and control gate overlying sad channel region and a portion of said source region, comprising the steps of: providing an erasing potential on said source to cause electrons to tunnel from said floating gate to said source; coupling a potential of said drain as feedback to said control gate, such that as said floating gate is discharged of said electrons, said drain potential increases proportionately to said discharge and said feedbback also causes a proportionate increase in potential at said control gate to counteract said erasing potential; wherein electron discharge is inhibited to prevent over-erasing of said EEPROM cell.

Claim 15

A method for self-limiting an electrical erase of an electrically programmable and electrically erasable read-only memory (EEPROM) cell having a source, drain, floating gate and control gate, wherein said source and drain are separated by a channel region, and said floating gate and control gate overlying said channel region and a portion of said source region, comprising the steps of: providing an erasing potential on said source to cause electrons to tunnel from said floating gate to said source; monitoring a potential of said drain, wherein as said electrons discharge from said floating gate, said drain potential increases proportionately; comparing said drain potential to a predetermined reference value; deactivating said erasing potential when said drain potential exceeds said predetermined reference value; wherein electron discharge is terminated to prevent over-erasing of said EEPROM cell.

Claim 16

A method for self-limiting an electrical erase of an electrically programmable and electrically erasable read-only memory (EEPROM) cell having a source, drain, floating gate and control gate, wherein said source and drain are separated by a channel region, and said floating gate and control gate overlying said channel region and a portion of said source region, comprising the steps of: providing an erasing potential on said source to cause electrons to tunnel from said floating gate to said source; monitoring a potential of said drain, wherein as said electrons discharge from said floating gate, said drain potential increases proportionately; comparing said drain potential to a predetermined reference value; deactivating said erasing potential when said drain potential exceeds said predetermined reference value; wherein electron discharge is terminated to prevent over-erasing of said EEPROM cell.