US4733371A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device with high voltage switch
Assignee: Mitsubishi Electric Corp
•
Filing: 1986-08-26
•
Granted: 1988-03-22
•
Expires: 2006-08-26
Abstract
Abstract A semiconductor memory device according to the present invention includes a first high-voltage switch (20) formed by a first transistor (21), a second transistor (22), a first capacitor (23) and a third transistor (24) and a second high-voltage switch (30) formed by a fourth transistor (31), a fifth transistor (32), a second capacitor (33) and a sixth transistor (34). In a write cycle, input data are stored in capacitors (25, 35). In an erase cycle, the second high-voltage switch (30) is driven by a clock signal (φ 2 ) to make the control gate line (4) rise at a high voltage. In a program cycle, the first high-voltage switch (20) is driven by a clock signal (φ 1 ) to make the bit line of the bit to be written with data "0" rise at a high voltge, and upon completion of the program cycle, charges stored in the capacitor (25) are discharged to reset a column latch. Thus, the device requires no inverter and may be provided with only one high voltage source.
Inventors
- 👤 Yasushi Terada
- 👤 Takeshi Nakayama
- 👤 Kazuo Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:34
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
229 words
A semiconductor memory device comprising bit lines, control gate lines, a high voltage source and first and second high-voltage switches, said first high-voltage switch including: a first transistor having a drain connected to said high-voltage source and a gate connected to said bit line, a second transistor having a drain connected to said bit line and a gate and a source connected to the source of said first transistor, a first capacitor having an end connected to the source of said first transistor and said gate and source of said second transistor, and a third transistor having a drain connected to the other end of said first capacitor, a gate connected to said bit line and a source applied with a first clock signal, said second high-voltage switch including: a fourth transistor having a drain connected to said high voltage source and a gate connected to said control gate line, a fifth transistor having a drain connected to said control gate line and a source connected to the source of said fourth transistor, a second capacitor having an end connected to said source of said fourth transistor and said gate and source of said fifth transistor, and a sixth transistor having a drain connected to the other end of said second capacitor, a gate connected to said control gate line and a source supplied with a second clock signal.
Claim 2
Dependent Claim
229 words
A semiconductor memory device comprising bit lines, control gate lines, a high voltage source and first and second high-voltage switches, said first high-voltage switch including: a first transistor having a drain connected to said high-voltage source and a gate connected to said bit line, a second transistor having a drain connected to said bit line and a gate and a source connected to the source of said first transistor, a first capacitor having an end connected to the source of said first transistor and said gate and source of said second transistor, and a third transistor having a drain connected to the other end of said first capacitor, a gate connected to said bit line and a source applied with a first clock signal, said second high-voltage switch including: a fourth transistor having a drain connected to said high voltage source and a gate connected to said control gate line, a fifth transistor having a drain connected to said control gate line and a source connected to the source of said fourth transistor, a second capacitor having an end connected to said source of said fourth transistor and said gate and source of said fifth transistor, and a sixth transistor having a drain connected to the other end of said second capacitor, a gate connected to said control gate line and a source supplied with a second clock signal.
Claim 3
Dependent Claim
116 words
A semiconductor memory device in accordance with claim 1, wherein said first high-voltage switch includes a seventh transistor having a gate supplied with a third clock signal, a drain to which said bit line is connected and a source to which said gate of said first transistor, said drain of said second transistor and said gate of said third transistor are connected, and said second high-voltage switch includes an eighth transistor having a gate supplied with a fourth clock signal, a drain to which said control gate line is connected and a source to which said gate of said fifth transistor, said drain of said sixth transistor and said gate of said seventh transistor are connected.
Claim 4
Dependent Claim
73 words
A semiconductor memory device in accordance with claim 2, wherein said first high-voltage switch includes a ninth transistor having a drain connected to said gate of said third transistor, a gate supplied with a first reset signal and a grounded source, and said second high-voltage switch includes a tenth transistor having a drain connected to said gate of said seventh transistor, a gate supplied with a second reset signal and a grounded source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-22 | 1991-09-21 | 1992-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-22 | 1995-09-21 | 1996-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-22 | 1999-09-21 | 2000-03-22 | $7700.00 | Window Closed / Lapsed |