Patent US5479033A successfully refreshed from Google Patents.
US5479033A
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Complementary junction heterostructure field-effect transistor
Assignee: National Technology and Engineering Solutions of Sandia LLC
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Filing: 1994-05-27
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Granted: 1995-12-26
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Expires: 2014-05-27
Abstract
Abstract A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.
Inventors
- 👤 Albert G. Baca
- 👤 Timothy J. Drummond
- 👤 Perry J. Robertson
- 👤 Thomas E. Zipperian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:34
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D30/00; H10D30/80; H10D30/801; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/02; H10D84/05
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
182 words
An integrated circuit comprising: (a) a compound semiconductor substrate having a plurality of epitaxially grown layers formed thereon, the layers including a buffer layer on the substrate, at least one first conducting channel layer above the buffer layer, a high bandgap layer above the first conducting channel layer and having a bandgap higher than the bandgap of the first conducting channel layer, and a first gate layer above the higher-bandgap layer; (b) at least one p-channel junction heterostructure field-effect transistor formed in the epitaxial layers, the p-channel transistor further comprising a first drain, a first source, and a first gate, and a plurality of electrodes thereupon; (c) at least one n-channel junction heterostructure field-effect transistor formed in the buffer layer, the n-channel transistor being located proximate to the p-channel transistor and in a region wherein the epitaxial layers above the buffer layer are removed, the n-channel transistor further comprising a second drain, a second source, and a second gate, and a plurality of electrodes thereupon; and (d) at least one isolation region formed in the substrate between the p-channel and n-channel transistors.
Claim 2
Dependent Claim
182 words
An integrated circuit comprising: (a) a compound semiconductor substrate having a plurality of epitaxially grown layers formed thereon, the layers including a buffer layer on the substrate, at least one first conducting channel layer above the buffer layer, a high bandgap layer above the first conducting channel layer and having a bandgap higher than the bandgap of the first conducting channel layer, and a first gate layer above the higher-bandgap layer; (b) at least one p-channel junction heterostructure field-effect transistor formed in the epitaxial layers, the p-channel transistor further comprising a first drain, a first source, and a first gate, and a plurality of electrodes thereupon; (c) at least one n-channel junction heterostructure field-effect transistor formed in the buffer layer, the n-channel transistor being located proximate to the p-channel transistor and in a region wherein the epitaxial layers above the buffer layer are removed, the n-channel transistor further comprising a second drain, a second source, and a second gate, and a plurality of electrodes thereupon; and (d) at least one isolation region formed in the substrate between the p-channel and n-channel transistors.
Claim 3
Dependent Claim
13 words
The integrated circuit in claim 1 in which the substrate is gallium arsenide.
Claim 4
Dependent Claim
21 words
The integrated circuit in claim 1 in which the at least one first conducting channel layer is a strained quantum-well layer.
Claim 5
Dependent Claim
18 words
The integrated circuit in claim 3 in which the strained quantum-well layer is an indium gallium arsenide layer.
Claim 6
Dependent Claim
15 words
The integrated circuit in claim 1 in which the buffer layer includes a leakage barrier.
Claim 7
Dependent Claim
16 words
The integrated circuit in claim 5 in which the leakage barrier is a semiconductor p-n junction.
Claim 8
Dependent Claim
24 words
The integrated circuit in claim 5 in which the leakage barrier forms the second gate and a second conducting channel of the n-channel transistor.
Claim 9
Dependent Claim
15 words
The integrated circuit in claim 5 in which the leakage barrier is modulation doping layer.
Claim 10
Dependent Claim
29 words
The integrated circuit in claim 5 in which the leakage barrier is formed from a semiconductor material having a bandgap higher than the bandgap of the first conducting channel.
Claim 11
Dependent Claim
16 words
The integrated circuit in claim 1 in which the high bandgap layer includes modulation doping means.
Claim 12
Dependent Claim
17 words
The integrated circuit in claim 1 in which the high bandgap layer includes a strain compensation region.
Claim 13
Dependent Claim
19 words
The integrated circuit in claim 1 in the form of a plurality of interconnected p-channel transistors and n-channel transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-25 | 1999-06-26 | 1999-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-25 | 2003-06-26 | 2003-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-25 | 2007-06-26 | 2007-12-26 | $7700.00 | Window Closed / Lapsed |