US5031007A
Expired / Lapsed
US
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SLS complementary logic devices with increase carrier mobility
Assignee: National Technology and Engineering Solutions of Sandia LLC
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Filing: 1990-10-26
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Granted: 1991-07-09
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Expires: 2010-10-26
Abstract
Abstract In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated.
Inventors
- 👤 Roger J. Chaffin
- 👤 Gordon C. Osbourn
- 👤 Thomas E. Zipperian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:55
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/4732; H10D62/00; H10D62/80; H10D62/81; H10D62/815; H10D62/8161; H10D62/8162; H10D62/8164; H10D84/00; H10D84/80; H10D84/86
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
74 words
In a complementary logic semiconductor device comprising at least one n-FET and at least one p-FET, the improvement wherein said p-FET is a strained layer superlattice comprising alternating quantum well and barrier layers of Group III/V semiconductors, said quantum well layers having a larger lattice constant than said barrier layers, said quantum well layers possess hole carriers having mobilities increased over those in the compositions of said quantum well layers when in bulk form.
Claim 2
Dependent Claim
74 words
In a complementary logic semiconductor device comprising at least one n-FET and at least one p-FET, the improvement wherein said p-FET is a strained layer superlattice comprising alternating quantum well and barrier layers of Group III/V semiconductors, said quantum well layers having a larger lattice constant than said barrier layers, said quantum well layers possess hole carriers having mobilities increased over those in the compositions of said quantum well layers when in bulk form.
Claim 3
Dependent Claim
13 words
The device of claim 1 wherein the FET's are Schottky-barrier, depletion mode FET's.
Claim 4
Dependent Claim
18 words
The device of claim 1, wherein the quantum well layers have a thickness less than about 100 angstroms.
Claim 5
Dependent Claim
29 words
The device of claim 1, further comprising, as a substrate for said superlattice, a semiconductor material having a lattice constant which does not substantially match that of said superlattice.
Claim 6
Dependent Claim
30 words
The device of claim 1 wherein said quantum well layer consists of In x Ga 1-x As and said barrier layer consists of In y Ga 1-y As, where x>y.
Claim 7
Dependent Claim
27 words
The device of claim 1 wherein said quantum well layer consists of InAs x Sb 1-x and said barrier layer consists of In y Ga 1-y As.
Claim 8
Dependent Claim
28 words
The device of claim 1 wherein said quantum well layer consists of In x Ga 1-x As and said barrier layer consists of Al y Ga 1-y As.
Claim 9
Dependent Claim
81 words
In a complementary logic semiconductor device comprising at least one n-FET and at least one p-FET, the improvement wherein said p-FET is a strained quantum well structure comprising a single quantum well layer of Group III/V semiconductors sandwiched between two bulk material layers, said quantum well layer having a larger lattice constant than said bulk material layers, said quantum well layer possesses hole carriers having mobilities increased over those in the compositions of said quantum well layer when in bulk form.
Claim 10
Dependent Claim
81 words
In a complementary logic semiconductor device comprising at least one n-FET and at least one p-FET, the improvement wherein said p-FET is a strained quantum well structure comprising a single quantum well layer of Group III/V semiconductors sandwiched between two bulk material layers, said quantum well layer having a larger lattice constant than said bulk material layers, said quantum well layer possesses hole carriers having mobilities increased over those in the compositions of said quantum well layer when in bulk form.
Claim 11
Dependent Claim
26 words
The device of claim 8 wherein said quantum well layer consists of In x Ga 1-x As and said sandwiching bulk layers each consist of GaAs.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-07-08 | 1995-01-07 | 1995-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-08 | 1999-01-07 | 1999-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-08 | 2003-01-07 | 2003-07-09 | $7700.00 | Window Closed / Lapsed |