US4117587A
Expired / Lapsed
US
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Negative-resistance semiconductor device
Assignee: Panasonic Holdings Corp
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Filing: 1976-08-06
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Granted: 1978-10-03
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Expires: 1996-08-06
Abstract
Abstract A pair of field-effect transistors (hereinafter referred to as FETs) of p-channel type and n-channel type, respectively, both to be electrically actuated in a depletion mode, are formed on a single semiconductor substrate, for instance, a single silicon substrate, and both sources or both drains are connected to each other, or the source of one FET and the drain of the other FET are connected to each other, whereby the pair of FETs are series-connected, and the gate electrode of each FET is connected to the drain electrode or the source electrode that is not series connected in the above-mentioned way, respectively, of the other FET. The device is characterized in that each FET has each back-gate electrode region behind the channel. Preferably, such back-gate regions are high-doped diffused regions. When a voltage of specified range is applied across both non-series-connected electrodes, i.e., the two external terminals, the resulting voltage-current characteristic presents a so-called dynatron-type characteristic, producing a negative-resistance phenomenon over a fairly wide range of applied voltage. Since this device is, as seen from outside as one device, a two-terminal device constituted on a single substrate comprising FETs with back-gate electrode, it is not only fit to be highly integrated but also able to produce a state of virtually zero value of cut-off current. Consequently, this device can be utilized for switching, memorization, large amplitude oscillation, and other various uses, with low Vth2 value.
Inventors
- 👤 Gota Kano
- 👤 Hitoo Iwasa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:09
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/36; G11C11/40; G11C11/41; G11C11/412; H10; H10D; H10D84/00; H10D84/01; H10D84/80; H10D84/87; G11C2211/00; G11C2211/56; G11C2211/561; G11C2211/5614
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
239 words
A method of making negative-resistance semiconductor devices of the type comprising two complimentary depletion type junction field effect transistors (FETs) interconnected together and the respective gates of said FETs are connected to the drain of the other FET, the method comprising the step of: forming diffused separation regions in an epitaxial region of a first conductivity type formed on a substrate of a second conductivity type, in a maner such that said diffused separation regions penetrate and hence divide said epitaxial region to form at least two islands which are isolated from each other by p-n junctions, forming a diffused well region of said second conductivity type in one of said islands, depositing shaped members of high concentration donor and of high concentration acceptor on specified portions of surfaces of the other one of said island regions and of said diffused well region, said specified portions being relatively disposed corresponding to the respective gates, drains and sources of said FETs, heat treating for simultaneously diffusing from said members of high concentration donor and said members of high concentration acceptor to form n + -regions and p + -regions, respectively, and thereby the gate, source and drain regions of said FETs, forming contact electrodes to said gate, drain and source regions; and forming electrical connections between the respective source regions of said FETs and between the respective gate regions of each FET to the drain region of the other FET.
Claim 2
Independent Claim
239 words
A method of making negative-resistance semiconductor devices of the type comprising two complimentary depletion type junction field effect transistors (FETs) interconnected together and the respective gates of said FETs are connected to the drain of the other FET, the method comprising the step of: forming diffused separation regions in an epitaxial region of a first conductivity type formed on a substrate of a second conductivity type, in a maner such that said diffused separation regions penetrate and hence divide said epitaxial region to form at least two islands which are isolated from each other by p-n junctions, forming a diffused well region of said second conductivity type in one of said islands, depositing shaped members of high concentration donor and of high concentration acceptor on specified portions of surfaces of the other one of said island regions and of said diffused well region, said specified portions being relatively disposed corresponding to the respective gates, drains and sources of said FETs, heat treating for simultaneously diffusing from said members of high concentration donor and said members of high concentration acceptor to form n + -regions and p + -regions, respectively, and thereby the gate, source and drain regions of said FETs, forming contact electrodes to said gate, drain and source regions; and forming electrical connections between the respective source regions of said FETs and between the respective gate regions of each FET to the drain region of the other FET.
Claim 3
Independent Claim
311 words
A method of making a negative-resistance semiconductor device of the type comprising two complementary depletion type junction field effect transistors (FETs) interconnected together and the respective gates of said FETs are connected to the drain of the other FET, the method comprising the steps of: forming p + -type diffused separation regions in an n-type epitaxial region formed on a p-type substrate, in a manner such that said diffused separation regions penetrate and hence divide said epitaxial region to form at least a first and a second island which are isolated from each other by p-n junctions, forming a p-type diffused region in a second one of said island regions; depositing a region of high concentration acceptor for forming a gate in said first island region and simultaneously depositing a pair of regions of high concentration acceptor for forming source and drain in said p-type diffused region, depositing a pair of regions of high concentration donor for forming source and drain in said first island region and simultaneously depositing a region of high concentration donor for forming a gate, heat treating for simultaneusly diffusing from said regions of high concentration donor and said regions of high concentration acceptor, thereby to form the source, drain and gate regions of an n-channel FET formed in said first island region and to form the same of a p-channel FET formed in said diffused region, said heat treating being controlled in a manner that depth of said p + -type region formed by diffusion from said acceptor being smaller than the depth of said first island region and depth of said n + -type region being smaller than the depth of said diffused region, and forming electrical connections between the source of one FET to the source of the other FET and between the respective gates of each FET and the drain of the other.
Claim 4
Independent Claim
311 words
A method of making a negative-resistance semiconductor device of the type comprising two complementary depletion type junction field effect transistors (FETs) interconnected together and the respective gates of said FETs are connected to the drain of the other FET, the method comprising the steps of: forming p + -type diffused separation regions in an n-type epitaxial region formed on a p-type substrate, in a manner such that said diffused separation regions penetrate and hence divide said epitaxial region to form at least a first and a second island which are isolated from each other by p-n junctions, forming a p-type diffused region in a second one of said island regions; depositing a region of high concentration acceptor for forming a gate in said first island region and simultaneously depositing a pair of regions of high concentration acceptor for forming source and drain in said p-type diffused region, depositing a pair of regions of high concentration donor for forming source and drain in said first island region and simultaneously depositing a region of high concentration donor for forming a gate, heat treating for simultaneusly diffusing from said regions of high concentration donor and said regions of high concentration acceptor, thereby to form the source, drain and gate regions of an n-channel FET formed in said first island region and to form the same of a p-channel FET formed in said diffused region, said heat treating being controlled in a manner that depth of said p + -type region formed by diffusion from said acceptor being smaller than the depth of said first island region and depth of said n + -type region being smaller than the depth of said diffused region, and forming electrical connections between the source of one FET to the source of the other FET and between the respective gates of each FET and the drain of the other.
Claim 5
Dependent Claim
51 words
The method of claim 1, wherein aid epitaxial growth region is n-type region of 3 to 8μm thickness and 5×10 14 to 5×10 15 atoms/cm 3 surface concentration, said diffused region is p-type region of 0.5 to 5μm thickness and 5×10 15 to 1×10 17 atoms/cm 3 concentration at the surface.
Claim 6
Independent Claim
337 words
A method of making a negative-resistance semi-conductor device of the type comprising complementary depletion type junction field effect transistors (FETs) interconnected such that the sources of said FETs are connected together, and the gate of each of said FETs is connected to the drain of the other, said method comprising the steps of: forming diffused separation regions in an epitaxial region of a first conductivity type formed on a substrate of a second conductivity type, said separation regions penetrating said epitaxial region to divide said epitaxial region and form thereby at least two islands isolated from each other by p-n junctions; forming a diffused well region of said second conductivity type in one of said islands; vapor-depositing a first, second and third shaped pellet of high carrier concentration material of said second conductivity type, said first and second pellets being disposed spaced apart on the surface of said well region, and third pellet being disposed on the surface of a second island different than said island containing said well region; vapor-depositing fourth, fifth and sixth shaped pellets of higher carrier concentration material of said first conductivity type, said fourth pellet being disposed between said first and second pellets on the surface of said well region, and said fifth and sixth pellets being formed adjacent opposite sides of said third pellet on the surface of said second island; heat treating for simultaneously diffusing said first, second, and fourth pellets into said well region and said third, fifth and sixth pellets into said epitaxial region and well region to simultaneously form thereby the drain, source and gate regions of a first FET and the gate, source and drain regions of a second FET complementary to said first FET; forming contact electrodes on the surfaces of the respective gate, source and drain regions of said first and second FETs; and forming electrical connections between the respective source regions of said first and second FETs, and between the respective gate regions of said FETs and the drain region of the other.
Claim 7
Independent Claim
337 words
A method of making a negative-resistance semi-conductor device of the type comprising complementary depletion type junction field effect transistors (FETs) interconnected such that the sources of said FETs are connected together, and the gate of each of said FETs is connected to the drain of the other, said method comprising the steps of: forming diffused separation regions in an epitaxial region of a first conductivity type formed on a substrate of a second conductivity type, said separation regions penetrating said epitaxial region to divide said epitaxial region and form thereby at least two islands isolated from each other by p-n junctions; forming a diffused well region of said second conductivity type in one of said islands; vapor-depositing a first, second and third shaped pellet of high carrier concentration material of said second conductivity type, said first and second pellets being disposed spaced apart on the surface of said well region, and third pellet being disposed on the surface of a second island different than said island containing said well region; vapor-depositing fourth, fifth and sixth shaped pellets of higher carrier concentration material of said first conductivity type, said fourth pellet being disposed between said first and second pellets on the surface of said well region, and said fifth and sixth pellets being formed adjacent opposite sides of said third pellet on the surface of said second island; heat treating for simultaneously diffusing said first, second, and fourth pellets into said well region and said third, fifth and sixth pellets into said epitaxial region and well region to simultaneously form thereby the drain, source and gate regions of a first FET and the gate, source and drain regions of a second FET complementary to said first FET; forming contact electrodes on the surfaces of the respective gate, source and drain regions of said first and second FETs; and forming electrical connections between the respective source regions of said first and second FETs, and between the respective gate regions of said FETs and the drain region of the other.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-02 | 1982-04-03 | 1982-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-02 | 1986-04-03 | 1986-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-02 | 1990-04-03 | 1990-10-03 | $7700.00 | Window Closed / Lapsed |