Bus interface state machines with independent access to memory, processor and registers for concurrent processing of different types of requests

Claim 2

A processing unit for processing a plurality of different types of system bus transactions, said processing unit being tightly coupled to a system bus which is operated according to a predetermined protocol, said processing unit including a microprocessor, a local memory tightly coupled to said microprocessor, a plurality of system visible registers and a system bus interface operatively coupled to said microprocessor, said local memory and said system visible registers for receiving and transmitting different types of requests including read/write commands, input/output commands and external read memory commands, said system bus interface comprising: a first interface section coupled to said system bus and to said microprocessor for processing a first type of request corresponding to said read/write commands generated and transferred by said microprocessor to said system bus; a second interface section coupled to said local memory for processing a second type of request corresponding to said external read memory commands transferred to said local memory from said system bus; and, a third interface section coupled to said system bus in common to said plurality of system visible registers for processing a third type of request corresponding to said external input/output commands received from said system bus reading and writing different ones of said registers, said interface sections each including a state machine programmed for independently processing each command until receipt of either a signal from said system bus indicating a successful completion of said each command or until completion of a predetermined retry procedure specific to the type of command being executed as defined by said predetermined protocol of said system bus thereby enabling simultaneous independent processing of said plurality of different types of bus transactions by said processing unit.

Claim 3

The processing unit of claim 1 wherein each of said state machines includes a number of programmable array logic (PAL) circuits, said number of PAL circuits being programmed to include a number of unique retry procedures for each command processed by corresponding interface section.

Claim 4

The processing unit of claim 2 wherein said number of PAL circuits of said first interface section operate to initiate a retry operation in response to receiving a wait signal from said system bus or a negative response if processing a predetermined type of memory command or terminate command processing upon receipt of a negative response to an input/output command.

Claim 5

The processing unit of claim 3 wherein said predetermined type of memory command corresponds to a memory lock command.

Claim 6

The processing unit of claim 2 wherein said number of PAL circuits of said third interface section operate to signal completion said command in response to an acknowledgement signal and to initiate a retry operation in response to either a negative response or a wait response which is treated as illegal according to said predetermined protocol.

Claim 7

The processing unit of claim 2 wherein said number of PAL circuits of said second interface section operate to initiate a retry operation in response to a negative response or wait response when processing a predetermined type of command requiring several system bus cycles of operation which was not completed and to set an indicator upon receiving an illegal response from said system bus.

Claim 8

The processing unit of claim 2 wherein one of said number of PAL circuits of each interface section is programmed to sequence through a number of preestablished states for completing the execution of each of said commands received by said interface section.

Claim 9

The processing unit of claim 7 wherein said one PAL circuit of each of said interface sections starts operating in a first one of said preestablished states corresponding to an idle state and in response to each command received by said interface, sequences to a second one of said preestablished states corresponding to a request state.

Claim 10

The processing unit of claim 8 wherein said one PAL circuit of each of said interface sections sequences from said second preestablished state to a third preestablished state corresponding to a second idle state upon issuing said command to said system bus.

Claim 11

The processing unit of claim 9 wherein said one PAL circuit of said first and second interface sections sequences from said third preestablished state to a fourth preestablished state corresponding to a cycle over state for signaling the termination of processing said command.

Claim 12

The processing unit of claim 1 wherein said unit further includes a clock generator for generating a clock reference signal for synchronizing the operations of each of said interface sections enabling the simultaneous processing of commands by said interface section.

Claim 13

The processing unit of claim 1 wherein said third interface section includes a send bus and a receive bus respectively for connecting said plurality of system visible registers to said system bus for reading out information to said system bus and writing information into each of said registers from said system bus.

Claim 14

A processing unit which tightly couples to a system bus which is operated according to a predetermined protocol, said processing unit including a microprocessor, a local memory tightly coupled to said microprocessor, a plurality of system visible registers and a system bus interface operatively coupled to said microprocessor, said local memory and to said plurality of system visible registers for receiving and transmitting to said system bus, different types of requests including processor read/write commands, external memory read commands and external input/output commands, said system bus interface comprising: a first interface section coupled to said microprocessor for processing said read/write commands generated by said microprocessor and transferred to said system bus which require execution of a first type of processing sequence for completion; a second interface section coupled to said local memory for processing said external read memory commands received from said system bus and transferred to said local memory which require execution of a second type of processing sequence for completion; a third interface section coupled to in common to said plurality of system visible registers for processing said external input/output commands received from said system bus for reading different ones of said registers which require execution of a third type of processing sequence for completion; and, each of said first, said second and said third interface sections including a state machine programmed for independently processing each command according to said first, second and third type of processing sequence, respectively, until receipt of a signal from said system bus indicating either a successful completion of said each command or until completion of a predetermined retry procedure specific to a type of command being executed as defined by said predetermined protocol of said system bus for enabling simultaneously independent processing of said different types of requests by said processing unit.

Claim 15

A processing unit which tightly couples to a system bus which is operated according to a predetermined protocol, said processing unit including a microprocessor, a local memory tightly coupled to said microprocessor, a plurality of system visible registers and a system bus interface operatively coupled to said microprocessor, said local memory and to said plurality of system visible registers for receiving and transmitting to said system bus, different types of requests including processor read/write commands, external memory read commands and external input/output commands, said system bus interface comprising: a first interface section coupled to said microprocessor for processing said read/write commands generated by said microprocessor and transferred to said system bus which require execution of a first type of processing sequence for completion; a second interface section coupled to said local memory for processing said external read memory commands received from said system bus and transferred to said local memory which require execution of a second type of processing sequence for completion; a third interface section coupled to in common to said plurality of system visible registers for processing said external input/output commands received from said system bus for reading different ones of said registers which require execution of a third type of processing sequence for completion; and, each of said first, said second and said third interface sections including a state machine programmed for independently processing each command according to said first, second and third type of processing sequence, respectively, until receipt of a signal from said system bus indicating either a successful completion of said each command or until completion of a predetermined retry procedure specific to a type of command being executed as defined by said predetermined protocol of said system bus for enabling simultaneously independent processing of said different types of requests by said processing unit.