Synchronous cache memory system incorporating tie-breaker apparatus for maintaining cache coherency using a duplicate directory

Claim 2

A private write through cache memory system included in one of a number of processing units for providing fast access to main memory information and which is updated in response to main memory write requests transferred over an asynchronous bus network, said cache memory system comprising: a main cache unit including a main directory having a plurality of addressable locations for storing addresses identifying which information words are stored in said main cache unit and for generating signals indicating whether or not information requested by said one processing unit is stored in said cache unit; a FIFO buffer circuit coupled to said bus network for storing at least one main memory request for information applied to said bus network; a duplicate directory having a plurality of addressable locations for storing a copy of said addresses stored in said main directory, said duplicate directory generating hit signals indicating whether or not said information being requested from main memory by a write request received from said FIFO buffer circuit, is stored in said cache unit; a first tie-breaker circuit connected to apply requests for access from said FIFO buffer circuit and said one processing unit to said duplicate directory for updating the status of said addresses during duplicate directory cycles of operation; a second tie-breaker circuit connected to apply requests for access from said duplicate directory and from said one processing unit to said main directory during main directory cycles of operation; and, timing means coupled to said directories, said tie-breaker circuits and said processing unit, said timing means generating clocking signals for synchronizing the operations of said directories, said cache store and said tie-breaker circuits with said one processing unit, each of said tie-breaker circuits including means responsive to said directory signals for detecting conditions during said directory cycles of operation which could cause cache incoherency, said means generating signals in response to said conditions for causing said directories to perform uninterrupted synchronized directory cycles of operation to maintain cache coherency.

Claim 3

The cache memory system of claim 1 wherein said first tie-breaker circuit includes replace request means in response to a FIFO write request and an invalidate request signal from said duplicate directory generated as a result of a signal indicative of a hit in which the address of the information specified by said FIFO request is detected as being stored in said main cache unit corresponding to a first one of said conditions, inhibits access to said duplicate directory by replace requests applied to said first tie-breaker circuit initiated by said one processing unit while simultaneously enabling said duplicate directory to perform an invalidate cycle of operation during which the address producing said hit signal is invalidated.

Claim 4

The cache memory system of claim 2 wherein each of said addresses stored in said duplicate directory includes a valid bit and said valid bit is set to a predetermined state of the corresponding address which produced said hit signal during said invalidate cycle of operation.

Claim 5

The cache memory system of claim 2 wherein said replace request means is connected to receive a replace request from said main directory, said replace request means generating signals in response to said replace request following completion of said invalidate cycle for enabling said duplicate directory to perform an allocate cycle of operation in which an address contained in a request from said one processing unit which resulted in said cache unit's generation of a miss indicating that the address is not stored in said cache unit, is used to update said duplicate directory.

Claim 6

The cache memory system of claim 4 wherein said replace request includes index and tag address bits and wherein said index and tag address bits of said replace request which produced said miss are written into one of said duplicate directory locations during said allocate cycle of operation.

Claim 7

The cache memory system of claim 1 wherein said duplicate directory further includes programmable logic circuit means connected to receive signals from said duplicate directory and said first and second tie-breaker circuits, said programmable logic circuit means in response to said signals generating invalidate entry request signals for inhibiting access by said requests initiated by said one processing unit.

Claim 8

The cache memory system of claim 6 wherein each said invalidate entry request signal is generated according to the following Boolean equation, wherein the symbols &, ! and # indicate and, inversion and OR operations respectively: INVENT=(HIT & !BYPASS # INVENT & !INVGNT) & !CPRSET where "HIT" corresponds to the hit signals generated by said duplicate directory, "BYPASS" indicates a bypass mode of operation and said INVENT signal is held on for a period of time defined by INVENT & !INVGNT where signal "INVENT" indicates the presence of an invalidate signal and signal "INVGNT" indicates that the invalidate request has been previously granted, and wherein signal "!CPRSET" indicates that no reset occurred.

Claim 9

The cache memory system of claim 2 wherein said first tie-breaker circuit further includes: a first clocked bistable circuit which is connected to be set to a predetermined state in response to a FIFO write request only during a first clock interval designated by a first one of said clocking signals, said first bistable circuit being connected to apply an input signal to said replace request means signalling a FIFO cycle of operation; and, a second clocked bistable circuit which is connected to be set to said predetermined state in response to one of said replace requests during a second clock interval designated by a second one of said clocking signals and to generate a replace granted output signal for signalling that access had been granted to said one processing unit request, said second one of said clock signals being out of phase with said first one of said clocking signals so as to serialize the processing of simultaneously applied requests.

Claim 10

The cache memory system of claim 8 wherein said first tie-breaker circuit further includes: a third clocked bistable circuit connected in series with said second clocked bistable circuit, said third clocked bistable circuit being switched to said predetermined state in response to said replace granted output signal during said first clock interval and generate a replace cycle output signal for signalling a replace cycle of operation; and output logic circuit means connected to said second and third clocked bistable circuits, said output logic circuit means in response to said replace granted output signal and said replace cycle output signal generating replace select address signal for applying said one processing unit request to said duplicate directory.

Claim 11

The cache memory system of claim 1 wherein said second tie-breaker circuit includes invalidate request means responsive to an invalidate request from said duplicate directory as a result of a signal indicative of a miss received from said duplicate directory and a request from said one processing unit generated as a result of a signal from said main directory indicative of a miss corresponding to a second one of said conditions which could cause cache incoherency, to inhibit access to said main directory by said invalidate request while simultaneously enabling said main directory to perform an allocate cycle of operation during which an address of said processing unit is written into one of said main directory locations.

Claim 12

The cache memory system of claim 10 wherein each of said addresses stored in said main directory includes a valid bit and said valid bit is set to a predetermined state in the corresponding location into which said address is written during said allocate cycle of operation.

Claim 13

The cache memory system of claim 10 wherein said invalidate request means is connected to receive an invalidate request from said duplicate directory, said invalidate request means following completion of said allocate cycle, generating signals in response to said invalidate request for enabling said main directory to perform an invalidate cycle of operation in which said address which resulted in the generation of said invalidate request is used to update said main directory.

Claim 14

The cache memory system of claim 12 wherein said invalidate request includes index address bits and a valid bit and wherein said valid bit of said index address bits which produced said hit is set to a predetermined state during said invalidate cycle of operation.

Claim 15

The cache memory system of claim 10 wherein said main directory further includes programmable logic circuit means connected to receive signals from said main directory and said first and second tie-breaker circuits, said programmable logic circuit means in response to said signals generating directory replace request signals for inhibiting access by said invalidate requests initiated by said duplicate directory.

Claim 16

The cache memory system of claim 14 wherein each said directory replace request signal is generated according to the following Boolean equation, wherein the symbols &, ! and # indicate and, inversion and OR operations respectively: DIRRPL=(!CPUW-R & MISS & !BYPASS # CPUCYC & DIRRPL) & !CPRSET) where "CPUW-R" corresponds to a signal generated from said one processing unit indicative of a cache read or write request, "MISS" indicates that a miss condition was detected by said main directory, "!BYPASS" indicates the absence of a bypass mode of operation, and wherein said DIRRPL signal is held on for a period of time defined by DIRRPL & CPUCYC wherein signal "DIRRPL" indicates that a replace operation is being performed and signal "CPUCYC" indicates that a CPU cycle is being performed by said second tie-breaker circuit, and wherein signal "!CPRSET" indicates that no reset occurred.

Claim 17

The cache memory system of claim 10 wherein said second tie-breaker circuit further includes: a first clocked bistable circuit which is connected to be set to a predetermined state in response to a request from said one processing unit only during a first clock interval designated by a first one of said clocking signals, said first bistable circuit being connected to apply an input signal to said replace request means signalling a CPU cycle of operation; and, a second clocked bistable circuit which is connected to be set to said predetermined state in response to one of said invalidate requests during a second clock interval designated by a second one of said clocking signals and to generate an invalidated granted output signal for signalling that access had been granted to said duplicate directory, said second one of said clock signals being out of phase with said first one of said clocking signals so as to serialize the processing of simultaneously applied requests.

Claim 18

The cache memory system of claim 16 wherein said second tie-breaker circuit further includes: a third clocked bistable circuit connected in series with said second clocked bistable circuit, said third clocked bistable circuit being switched to said predetermined state in response to said invalidate granted output signal during said first clock interval and generate an invalidate cycle output signal for signalling an invalidate cycle of operation; and output logic circuit means connected to said second and third clocked bistable circuits, said output logic circuit means in response to said invalidate granted output signal and said invalidate cycle output signal generating invalidate select address signals for applying said address to said main directory.

Claim 19

For use in a data processing system including a main memory shared by a number of processing units including input/output units connected in common to an asynchronous bus network which can assign bus cycles for accessing said shared main memory to different ones of said number of processing units for higher performance, a private write through cache memory system included in one of said number of processing units for providing fast access to main memory information and which is updated in response to each main memory write request issued by said one processing unit, said cache memory system comprising: a main cache store having a number of addressable locations for storing said main memory information needed by said one processing unit for performing its operations; a main directory having a plurality of addressable locations for storing addresses identifying which information words are stored in said main cache store, said main directory including address tag compare circuits for generating hit signals indicating when information requested by said one processing unit is stored in said cache store; a FIFO buffer circuit coupled to said but network for storing main memory requests for information applied to said bus network during each assigned bus cycle of operation; a duplicate directory having a plurality of addressable locations for storing a copy of said addresses stored in said main directory, said duplicate directory including address tag compare circuits for generating hit signals indicating when said information being requested from main memory by a write request received from said FIFO buffer circuit is stored in said cache store; a first tie-breaker circuit connected to apply requests received from said FIFO buffer circuit and said one processing unit to said duplicate directory for updating the status of said addresses during duplicate directory cycles of operation; a second tie-breaker circuit connected to apply requests received from said duplicate directory and from said one processing unit to said main directory during main directory cycles of operation; and, timing means generating state and clock signals for synchronizing the operations of said directories, said cache store and said tie-breaker with said one processing unit, each of said tie-breaker circuits including means responsive to said hit signals for detecting conditions during predetermined ones of said directory cycles of operation associated therewith which could cause cache incoherency to generate signals for causing said main and duplicate directories to perform uninterrupted synchronized directory cycles of operation to maintain cache coherency.

Claim 20

For use in a data processing system including a main memory shared by a number of processing units including input/output units connected in common to an asynchronous bus network which can assign bus cycles for accessing said shared main memory to different ones of said number of processing units for higher performance, a private write through cache memory system included in one of said number of processing units for providing fast access to main memory information and which is updated in response to each main memory write request issued by said one processing unit, said cache memory system comprising: a main cache store having a number of addressable locations for storing said main memory information needed by said one processing unit for performing its operations; a main directory having a plurality of addressable locations for storing addresses identifying which information words are stored in said main cache store, said main directory including address tag compare circuits for generating hit signals indicating when information requested by said one processing unit is stored in said cache store; a FIFO buffer circuit coupled to said but network for storing main memory requests for information applied to said bus network during each assigned bus cycle of operation; a duplicate directory having a plurality of addressable locations for storing a copy of said addresses stored in said main directory, said duplicate directory including address tag compare circuits for generating hit signals indicating when said information being requested from main memory by a write request received from said FIFO buffer circuit is stored in said cache store; a first tie-breaker circuit connected to apply requests received from said FIFO buffer circuit and said one processing unit to said duplicate directory for updating the status of said addresses during duplicate directory cycles of operation; a second tie-breaker circuit connected to apply requests received from said duplicate directory and from said one processing unit to said main directory during main directory cycles of operation; and, timing means generating state and clock signals for synchronizing the operations of said directories, said cache store and said tie-breaker with said one processing unit, each of said tie-breaker circuits including means responsive to said hit signals for detecting conditions during predetermined ones of said directory cycles of operation associated therewith which could cause cache incoherency to generate signals for causing said main and duplicate directories to perform uninterrupted synchronized directory cycles of operation to maintain cache coherency.

Claim 21

The cache memory system of claim 18 wherein said first tie-breaker circuit includes replace request means in response to a FIFO write request and an invalidate request signal from said duplicate directory generated as a result of a hit signal from said address tag compare circuits indicative of a first one of said conditions, inhibits access to said duplicate directory by replace requests applied to said first tie-breaker circuit initiated by said one processing unit while simultaneously enabling said duplicate directory to perform an invalidate cycle of operation during which the address producing said hit signal is invalidated.

Claim 22

The cache memory system of claim 19 wherein each of said addresses stored in said duplicate directory includes a valid bit and said valid bit is set to a predetermined state of the corresponding address which produced said hit signal during said invalidate cycle of operation.

Claim 23

The cache memory system of claim 19 wherein said replace request means is connected to receive a replace request from said main directory, said replace request means generating signals in response to said replace request following completion of said invalidate cycle for enabling said duplicate directory to perform an allocate cycle of operation in which an address contained in a request from said one processing unit which did not result in said main directory address tag compare circuits generating said hit signals indicating a miss is used to update said duplicate directory.

Claim 24

The cache memory system of claim 21 wherein said replace request includes index and tag address bits and wherein said index and tag address bits of said replace request which produced said miss are written into one of said duplicate directory locations during said allocate cycle of operation.

Claim 25

The cache memory system of claim 18 wherein said duplicate directory further includes programmable logic circuit means connected to receive signals from said address tag compare circuits and to said first and second tie-breaker circuits, said programmable logic circuit means in response to said signals generating invalidate entry request signals for inhibiting access by said requests initiated by said one processing unit.

Claim 26

The cache memory system of claim 23 wherein each said invalidate entry request signal is generated according to the following Boolean equation, wherein the symbols &, ! and # indicate and, inversion and OR operations respectively: INVENT=(HIT & !BYPASS # INVENT & !INVGNT) & !CPRSET where "HIT" corresponds to the hit signals generated by said duplicate directory, "BYPASS" indicates a bypass mode of operation and said INVENT signal is held on for a period of time defined by INVENT & !INVGNT wherein signal "INVENT" indicates the presence of an invalidate signal and signal "INVGNT" indicates that the invalidate request has been previously granted and wherein signal "!CPRSET" indicates that no reset occurred.

Claim 27

The cache memory system of claim 19 wherein said first tie-breaker circuit further includes: a first clocked bistable circuit which is connected to be set to a predetermined state in response to a FIFO write request only during a first clock interval designated by a first one of said clocking signals, said first bistable circuit being connected to apply an input signal to said replace request means signalling a FIFO cycle of operation; and, a second clocked bistable circuit which is connected to be set to said predetermined state in response to one of said replace requests during a second clock interval designated by a second one of said clocking signals and to generate a replace granted output signal for signalling that access had been granted to said CP request, said second one of said clock signals being out of phase with said first one of said clocking signals so as to serialize the processing of simultaneously applied requests.

Claim 28

The cache memory system of claim 25 wherein said first tie-breaker circuit further includes: a third clocked bistable circuit connected in series with said second clocked bistable circuit, said third clocked bistable circuit being switched to said predetermined state in response to said replace granted output signal during said first clock interval and generate a replace cycle output signal for signalling a replace cycle of operation; and output logic circuit means connected to said second and third clocked bistable circuits, said output logic circuit means in response to said replace granted output signal and said replace cycle output signal generating replace select address signal for applying said one processing unit request to said duplicate directory.

Claim 29

The cache memory system of claim 18 wherein said second tie-breaker circuit includes invalidate request means in response to an invalidate request from said duplicate directory as a result of a hit signal from said address tag compare circuits and a request from said one processing unit generated as a result of the absence of a hit signal from said main directory address tag compare circuits indicative of a second one of said conditions which could cause cache incoherency, inhibits access to said main directory by said invalidate request while simultaneously enabling said main directory to perform an allocate cycle of operation during which an address of said processing unit is written into one of said main directory locations.

Claim 30

The cache memory system of claim 27 wherein each of said addresses stored in said main directory includes a valid bit and said valid bit is set to a predetermined state in the corresponding location into which said address is written during said allocate cycle of operation.

Claim 31

The cache memory system of claim 27 wherein said invalidate request means is connected to receive an invalidate request from said duplicate directory, said invalidate request means following completion of said allocate cycle generating signals in response to said invalidate request for enabling said main directory to perform an invalidate cycle of operation in which said address which resulted in the generation of said invalidate request is used to update said main directory.

Claim 32

The cache memory system of claim 29 wherein said invalidate request includes index address bits and a valid bit and wherein said valid bit of said index address bits which produced said hit is set to a predetermined state during said invalidate cycle of operation.

Claim 33

The cache memory system of claim 18 wherein said main directory further includes programmable logic circuit means connected to receive signals from said address tag compare circuits and said first and second tie-breaker circuits, said programmable logic circuit means in response to said signals generating directory replace request signals for inhibiting access by said invalidate requests initiated by said duplicate directory.

Claim 34

The cache memory system of claim 31 wherein each said directory replace request signal is generated according to the following Boolean equation, wherein the symbols &, ! and # indicate and, inversion and OR operations respectively: DIRRPL=(!CPUW-R & MISS & !BYPASS # CPUCYC & DIRRPL) & !CPRSET) where "CPUW-R" corresponds to a signal generated from said one processing unit indicative of a cache read or write request, "MISS" indicates that a miss condition was detected by said main directory, "!BYPASS" indicates the absence of a bypass mode of operation, and wherein said DIRRPL signal is held on for a period of time defined by DIRRPL & CPUCYC wherein signal "DIRRPL" indicates that a replace operation is being performed wherein signal "CPUCYC" indicates that a CPU cycle is being performed by said second tie-breaker circuit, and wherein signal "!CPRSET" indicates that no reset occurred.

Claim 35

The cache memory system of claim 18 wherein said second tie-breaker circuit further includes: a first clocked bistable circuit which is connected to be set to a predetermined state in response to a request from said one processing unit only during a first clock interval designated by a first one of said clocking signals, said first bistable circuit being connected to apply an input signal to said replace request means signalling a CPU cycle of operation; and, a second clocked bistable circuit which is connected to be set to said predetermined state in response to one of said invalidate requests during a second clock interval designated by a second one of said clocking signals and to generate an invalidated granted output signal for signalling that access had been granted to said duplicate directory, said second one of said clock signals being out of phase with said first one of said clocking signals so as to serialize the processing of simultaneously applied requests.

Claim 36

The cache memory system of claim 33 wherein said second tie-breaker circuit further includes: a third clocked bistable circuit connected in series with said second clocked bistable circuit, said third clocked bistable circuit being switched to said predetermined state in response to said invalidate granted output signal during said first clock interval and generate an invalidate cycle output signal for signalling an invalidate cycle of operation; and output logic circuit means connected to said second and third clocked bistable circuits, said output logic circuit means in response to said invalidate granted output signal and said invalidate cycle output signal generating invalidate select address signals for applying said address to said main directory.