Single chip communication data processor with direct memory access controller having a channel control circuit

Claim 2

An integrated communication data processor for use with a host processor and a main memory device, said integrated communication data processor comprising: an internal processing unit for executing communication processing in accordance with predetermined instructions; a receiving means for receiving serial data inputted to the integrated communication data processor and for transforming the serial data into parallel data; a receiving buffer means coupled to the receiving means for storing the parallel data and for providing the parallel data in units of bytes; and, a direct memory access control means for transmitting the parallel data stored in the receiving buffer means to the main memory device, wherein the direct access memory control means transmits the parallel data independently of the internal processing unit, the direct memory access control means including: an address register for storing address data transmitted by the host processor, said address data representing an address in the main memory device to which the parallel data will be transmitted; an increment means for incrementing the address data when a parallel data byte is transmitted to the main memory device; a byte count register for storing transfer byte count data transmitted by the host processor, said transfer byte count data representing the number of parallel data bytes to be transmitted to the main memory device; a decrement means for decrementing the transfer byte count data when one parallel data byte is transmitted; a control circuit means for overseeing the byte count data and for providing a status data based upon the transfer byte count data; a data assembler for assembling the parallel data in units of two bytes before said parallel data is transferred to the main memory device and wherein the control circuit means controls the data assembler; and, a status register means for storing the status data transmitted by the control circuit means, wherein said status data is polled by the internal processing unit.

Claim 3

The integrated communication data processor according to claim 1, wherein the direct memory access control means further comprises a register means for storing a command data transmitted by the internal processing unit, said command data representing an operation instruction of the direct memory access control means, and wherein the control circuit means further includes a decoder for decoding the command data.

Claim 4

An integrated communication data process for use with a host processor and a main memory comprising: an internal processing unit for executing communication processes in accordance with predetermined instructions; a receiving means for receiving a first serial data inputted to the integrated communication control processor and for transforming said first serial data into a first parallel data; a receiving buffer means coupled to the receiving means for storing the first parallel data; a transfer buffer means for storing a second parallel data; a transfer means for transforming said second parallel data into a second serial data and for transmitting the second serial data; a direct memory access controller having first channel portion in which the first parallel data is transmitted from the receiving means to the main memory device, the transmission occurring without internal processing unit control, and a second channel portion in which second parallel data stored in the main memory is transmitted to the transfer buffer means, the transmission occurring without internal processing unit control, wherein the first channel portion includes a first address register for storing a first address data transmitted by the host processor, said first address data representing an address in the main memory to which the first parallel data will be transmitted, and the second channel portion includes a second address register for storing a second address data transmitted by the host processor, said second address data representing an address in the main memory device at which the second parallel data is stored; a first byte register for storing a first transfer byte count transmitted by the host processor, said first transfer byte count representing a number of first parallel data bytes to be transmitted to the main memory device; a second byte register for storing a second transfer byte count data transmitted by the host processor, said second transfer byte count data representing a number of second parallel data bytes to be transmitted to the transfer buffer means; said direct memory access controller further having: an increment means for selectively incrementing the first or second address data when a corresponding first or second parallel data byte is transferred; a decrement means for decrementing the first or second transfer byte count data when a corresponding first or second parallel data byte is transferred; wherein the first channel portion further has: a first control circuit means for overseeing the first transfer byte count and for providing a first status data based upon the first transfer byte count data; a first status register for storing the first status data transmitted by the first control means, wherein the first status data is polled by the internal processing unit; and, wherein the second channel portion further has: a second control circuit means for overseeing the second transfer byte count and for providing a second status data based upon the second transfer byte count data; and, a second status register for storing the second status data transmitted by the second control circuit means, wherein the second status data is polled by the internal processing means.

Claim 5

An integrated communication data process for use with a host processor and a main memory comprising: an internal processing unit for executing communication processes in accordance with predetermined instructions; a receiving means for receiving a first serial data inputted to the integrated communication control processor and for transforming said first serial data into a first parallel data; a receiving buffer means coupled to the receiving means for storing the first parallel data; a transfer buffer means for storing a second parallel data; a transfer means for transforming said second parallel data into a second serial data and for transmitting the second serial data; a direct memory access controller having first channel portion in which the first parallel data is transmitted from the receiving means to the main memory device, the transmission occurring without internal processing unit control, and a second channel portion in which second parallel data stored in the main memory is transmitted to the transfer buffer means, the transmission occurring without internal processing unit control, wherein the first channel portion includes a first address register for storing a first address data transmitted by the host processor, said first address data representing an address in the main memory to which the first parallel data will be transmitted, and the second channel portion includes a second address register for storing a second address data transmitted by the host processor, said second address data representing an address in the main memory device at which the second parallel data is stored; a first byte register for storing a first transfer byte count transmitted by the host processor, said first transfer byte count representing a number of first parallel data bytes to be transmitted to the main memory device; a second byte register for storing a second transfer byte count data transmitted by the host processor, said second transfer byte count data representing a number of second parallel data bytes to be transmitted to the transfer buffer means; said direct memory access controller further having: an increment means for selectively incrementing the first or second address data when a corresponding first or second parallel data byte is transferred; a decrement means for decrementing the first or second transfer byte count data when a corresponding first or second parallel data byte is transferred; wherein the first channel portion further has: a first control circuit means for overseeing the first transfer byte count and for providing a first status data based upon the first transfer byte count data; a first status register for storing the first status data transmitted by the first control means, wherein the first status data is polled by the internal processing unit; and, wherein the second channel portion further has: a second control circuit means for overseeing the second transfer byte count and for providing a second status data based upon the second transfer byte count data; and, a second status register for storing the second status data transmitted by the second control circuit means, wherein the second status data is polled by the internal processing means.

Claim 6

The integrated communication control processor according to claim 3 wherein the first and second channel portions include a command register means for storing a corresponding first or second command data transmitted by the internal processing unit, said first or second command data representing an operation instruction for the corresponding first or second channel portion, and wherein the first and second control circuit means include a decoder means for decoding the corresponding first or second command data.

Claim 7

The integrated communication control processor according to claim 3 wherein the receiving buffer means provides the parallel data in units of bytes, wherein the first channel portion includes a first data assembler for assembling the first parallel data in units of two bytes before said parallel data is transferred to the main memory device, and wherein the first control circuit means controls the first data assembler operation.

Claim 8

The integrated communication control processor according to claim 3 wherein provided data is received by the direct memory access controller in units of two bytes from the main memory, wherein the second channel portion includes a data assembler means for disassembling the provided data into units of one byte before said data is transferred to the transfer buffer means, and wherein the second control circuit means controls the second data assembler.