Patent US5468992A successfully refreshed from Google Patents.
US5468992A
Expired / Lapsed
US
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Electronic circuit package including plural bare chips mounted on a single wiring substrate
Assignee: Rising Silicon Inc
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Filing: 1992-02-28
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Granted: 1995-11-21
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Expires: 2012-02-28
Abstract
Abstract An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wire bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer element. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, thereby making it possible to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line being formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line being formed on the other side of the wiring substrate.
Inventors
- 👤 Nobuyasu Kanekawa
- 👤 Hirokazu Ihara
- 👤 Masatsugu Akiyama
- 👤 Kiyoshi Kawabata
- 👤 Hisayoshi Yamanaka
- 👤 Tetsuya Okishima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:29
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/02; G11C5/04; G11C5/06; H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/65; H10W72/00; H10W90/00; H10W70/654; H10W70/656; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/541; H10W72/547; H10W72/851; H10W72/874; H10W72/884; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
136 words
An electronic circuit package comprising: a multilayer wiring substrate, wherein said multilayer wiring substrate includes internal wiring conductors; an insulating layer formed on a portion of a surface of said multilayer wiring substrate; a plurality of die bonding grounds formed on a surface of said insulating layer; a plurality of semiconductor bare chips formed on said die bonding ground; wiring pads formed on said semiconductor bare chips and on said multilayer wiring substrate along the periphery of said die bonding ground, wherein said semiconductor bare chips are connected to said wiring conductors through wire bonding between wire bonding pads formed on said semiconductor bare chips and the wiring substrate; wherein a portion of said multilayer wiring substrate under said die bonding ground is used as a via hole region for affecting connection between said wiring conductors.
Claim 2
Dependent Claim
136 words
An electronic circuit package comprising: a multilayer wiring substrate, wherein said multilayer wiring substrate includes internal wiring conductors; an insulating layer formed on a portion of a surface of said multilayer wiring substrate; a plurality of die bonding grounds formed on a surface of said insulating layer; a plurality of semiconductor bare chips formed on said die bonding ground; wiring pads formed on said semiconductor bare chips and on said multilayer wiring substrate along the periphery of said die bonding ground, wherein said semiconductor bare chips are connected to said wiring conductors through wire bonding between wire bonding pads formed on said semiconductor bare chips and the wiring substrate; wherein a portion of said multilayer wiring substrate under said die bonding ground is used as a via hole region for affecting connection between said wiring conductors.
Claim 3
Dependent Claim
56 words
An electronic circuit package according to claim 1, wherein said wiring conductors include conductors, each formed in a different wiring layer in said multilayer wiring substrate, wiring conductors between different wiring layers being connected through via holes in said via hole region and on said multilayer wiring substrate at the periphery of said die bonding ground.
Claim 4
Dependent Claim
53 words
An electronic circuit package according to claim 2, wherein said via holes are formed at the periphery of said die bonding ground and in said via hole region, and wherein via holes formed at the periphery of said die bonding ground and via holes formed in said via hole region are arranged alternately.
Claim 5
Dependent Claim
29 words
An electronic circuit package according to claim 3, wherein said semiconductor chips include a microprocessing unit and a checking unit for detecting errors and faults of said microprocessing unit.
Claim 6
Dependent Claim
36 words
An electronic circuit package according to claim 4, wherein said semiconductor chips include a random access memory and an error correction code unit for detecting errors of said random access memory and for correcting said errors.
Claim 7
Dependent Claim
26 words
An electronic circuit package according to claim 5, wherein one of said checking unit and said error correction code unit is included in a gate array.
Claim 8
Dependent Claim
16 words
An electronic circuit package according to claim 1, wherein said semiconductor chips include a gate array.
Claim 9
Dependent Claim
146 words
An electronic circuit package, comprising: a multilayer wiring substrate; a plurality of semiconductor bare chips which are bare-chip mounted on said wiring substrate; a bus line which is formed on said wiring substrate; wire bonding pads formed on the semiconductor bare chip and wiring substrate; and an insulating layer formed on a portion of a surface of said wiring substrate and a die bonding ground formed on a surface of said insulating layer, in order to use a portion of said multilayer wiring substrate under said die bonding ground as a wiring or via hole region, wherein at least one of said semiconductor chips is formed on said die bonding ground; wherein each of said plurality of semiconductor bare chips is electrically connected to said bus line through wire bonding connections between said wire bonding pads formed on the semiconductor bare chips and the wiring substrate.
Claim 10
Dependent Claim
146 words
An electronic circuit package, comprising: a multilayer wiring substrate; a plurality of semiconductor bare chips which are bare-chip mounted on said wiring substrate; a bus line which is formed on said wiring substrate; wire bonding pads formed on the semiconductor bare chip and wiring substrate; and an insulating layer formed on a portion of a surface of said wiring substrate and a die bonding ground formed on a surface of said insulating layer, in order to use a portion of said multilayer wiring substrate under said die bonding ground as a wiring or via hole region, wherein at least one of said semiconductor chips is formed on said die bonding ground; wherein each of said plurality of semiconductor bare chips is electrically connected to said bus line through wire bonding connections between said wire bonding pads formed on the semiconductor bare chips and the wiring substrate.
Claim 11
Dependent Claim
77 words
An electronic circuit package according to claim 8, further comprising an insulating layer formed on a portion of a surface of said multilayer wiring substrate and a die bonding ground formed on a surface of said insulating layer, in order to use a portion of said multilayer wiring substrate under said die bonding ground as a wiring or a via hole region, wherein at least one of said semiconductor chips is formed on said die bonding ground.
Claim 12
Dependent Claim
64 words
An electronic circuit package according to claim 8, wherein said bus line includes two data bus lines wherein predetermined chips of said semiconductor bare chips connected with one data bus line are formed on one side of said wiring substrate and others of said semiconductor bare chips connected with the other data bus line are formed on the other side of said wiring substrate.
Claim 13
Dependent Claim
27 words
An electronic circuit package according to claim 10, wherein said semiconductor bare chips connected to said data bus lines include random access memories and read only memories.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-20 | 2003-05-22 | 2003-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |