US4746966A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic-circuit layout for large-scale integrated circuits
Assignee: International Business Machines Corp
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Filing: 1985-10-21
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Granted: 1988-05-24
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Expires: 2005-10-21
Abstract
Abstract A VLSI chip has multiple annular rings of circuit cells, interspersed with annular wiring channels for interconecting the cells. Another wiring layer runs perpendicular to the rings. A central chip area contains all the I/O connections for the chip.
Inventors
- 👤 Joseph M. FitzGerald
- 👤 Pho H. Nguyen
- 👤 Robert R. Williams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:03
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/20; H10D; H10D84/00; H10D84/90; H10D84/998; H10D89/00; H10D89/10; H10D89/105; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W72/251
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
140 words
An integrated-circuit chip, comprising: a substrate having a central point substantially in the center of the area of said chip, having a single relatively small central area including said central point, and having a much larger peripheral area completely surrounding said central area; multiple signal-circuit cells and signal-interconnection means thereamong located in said peripheral area, said cells and interconnection means forming substantially all of the signal circuits and signal interconnections on said chip; a ring of multi-device input/output-circuit cells disposed about said central point in said central area; conductive means for connecting said signal-circuit cells in said peripheral area to said input/output cells in said central area; an array of off-chip contacts located within said central area, said array including substantially all of the off-chip contacts of said chip; conductive means for connecting said input/output-circuit cells to said off-chip contacts.
Claim 2
Dependent Claim
140 words
An integrated-circuit chip, comprising: a substrate having a central point substantially in the center of the area of said chip, having a single relatively small central area including said central point, and having a much larger peripheral area completely surrounding said central area; multiple signal-circuit cells and signal-interconnection means thereamong located in said peripheral area, said cells and interconnection means forming substantially all of the signal circuits and signal interconnections on said chip; a ring of multi-device input/output-circuit cells disposed about said central point in said central area; conductive means for connecting said signal-circuit cells in said peripheral area to said input/output cells in said central area; an array of off-chip contacts located within said central area, said array including substantially all of the off-chip contacts of said chip; conductive means for connecting said input/output-circuit cells to said off-chip contacts.
Claim 3
Dependent Claim
15 words
A chip according to claim 1, wherein said chip has a generally rectangular overall shape.
Claim 4
Dependent Claim
19 words
A chip according to claim 2, wherein said central area generally conforms to the overall shape of said chip.
Claim 5
Dependent Claim
41 words
A chip according to claim 1, wherein at least some of said input/output cells have a length in the direction transverse to said ring and a width in the direction along said ring such that said length substantially exceeds said width.
Claim 6
Dependent Claim
40 words
A chip according to claim 4, wherein substantially all of said input/output cells have a length in the direction transverse to said ring and a width in the direction along said ring such that said length substantially exceeds said width.
Claim 7
Dependent Claim
24 words
A chip according to claim 1, wherein said ring comprises multiple arms, each arm comprising multiple input/output cells disposed in a substantially straight line.
Claim 8
Dependent Claim
29 words
A chip according to claim 1, wherein said ring comprises pairs of said input/output cells, the cells in said pairs being disposed radially with respect to said central point.
Claim 9
Dependent Claim
39 words
A chip according to claim 1, wherein said chip further comprises: first and second conductive layers for containing said signal-interconnection means; a third conductive layer for containing said conductive means for interconnecting said input/output cells to said off-chip contacts.
Claim 10
Dependent Claim
27 words
A chip according to claim 8, wherein said third conductive layer contains substantially all of said conductive means for interconnecting said input/output cells to said off-chip contacts.
Claim 11
Dependent Claim
19 words
A chip according to claim 8, wherein said third conductive layer further contains a portion of said signal-interconnection means.
Claim 12
Dependent Claim
21 words
A chip according to claim 10, wherein said signal-interconnection means portion is substantially confined to said peripheral area of said chip.
Claim 13
Dependent Claim
29 words
A chip according to claim 8, wherein said input/output cells include signal connections within said input/output cells, said intra-cell connections being confined to said first and second conductive layers.
Claim 14
Dependent Claim
31 words
A chip according to claim 12, wherein at least some of said signal connections within said input/output cells extend to a wiring bay located outside said ring in said central area.
Claim 15
Dependent Claim
54 words
A chip according to claim 1, wherein said chip further comprises: a pair of large-area power planes in said central area; means for connecting said planes to certain ones of said off-chip contacts in said central area; multiple radial power straps extending from said power planes to said input/output cells for distributing power thereto.
Claim 16
Dependent Claim
20 words
A chip according to claim 14, further comprising a pair of ring-shaped power busses connected to said radial power straps.
Claim 17
Dependent Claim
28 words
A chip according to claim 15, further comprising multiple peripheral power busses extending from said ring-shaped power busses and connected to said signal-circuit cells in said peripheral area.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-24 | 1991-11-23 | 1992-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-24 | 1995-11-23 | 1996-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-24 | 1999-11-23 | 2000-05-24 | $7700.00 | Window Closed / Lapsed |