Integrated circuit including test portion and method for making

Claim 2

An integrated circuit die including a crystalline semiconductor chip having a plurality of resistors, bipolar transistors and other electronic circuit elements interconnected to form the principal circuit of said die and a plurality of metal pads on said chip being connected to and providing electrical access to various points of said principal circuit, wherein the improvement comprises: a separate test circuit comprised of electrical circuit elements including at least one bipolar transistor, at least one resistor and other metal pads that are adapted to be contacted by probing, said other pads being connected to and providing separate electrical access to various points of said test circuit, all of said electrical circuit elements of said test circuit being formed at only one electrically isolated pocket of said semiconductor chip.

Claim 3

The integrated circuit die of claim 1 wherein said at least one bipolar transistor of said test circuit has been formed altogether simultaneously with at least some of said principal circuit transistors.

Claim 4

The integrated circuit die of claim 1 wherein a doped substrate portion of said chip is of one polarity type and said pocket is of the opposite polarity type, said at least one transistor being a vertical transistor of a first polarity type, said test circuit additionally comprising a lateral bipolar transistor and another one of said principal circuit transistors also being a lateral bipolar transistor having been altogether simultaneously formed with said lateral test circuit transistor.

Claim 5

The integrated circuit die of claim 3 wherein in said test circuit a first, second, third and fourth of said other metal pads are ohmically connected, respectively, to the emitter of said lateral transistor, to said pocket, to the base of said vertical transistor and to the emitter of said vertical transistor.

Claim 6

The integrated circuit die of claim 4 additionally comprising an isolation wall of said one polarity type formed in said chip about said pocket, said fourth terminal pad being additionally connected to said one type isolation wall and thus to said one type substrate portion, and said one pocket additionally includes a buried layer of said type at the interface of said pocket and said substrate portion, said buried layer lying under said vertical test circuit transistor and away from the portion of said interface that is under said lateral test circuit transistor so that said one type substrate portion may serve as another collector in said lateral test circuit transistor, to which collector electrical access may be had at said fourth terminal.

Claim 7

The integrated circuit die of claim 1 wherein at least one of said principal circuit resistors and said one test circuit resistor are of the diffused type having been formed all together simultaneously; and additionally comprising an insulative layer formed over the outer surface of said die; and another of said test circuit resistors being a thin film type formed on said insulative layer; and another of said principal circuit resistors also being a thin film type having been formed altogether simultaneously with said thin film test circuit resistor.

Claim 8

The integrated circuit die of claim 6 wherein within said test circuit said diffused resistor and said thin film resistors are connected, respectively, across the base emitter junctions of said vertical and said lateral transistors.

Claim 9

An integrated circuit wafer consisting essentially of a matrix of crystalline semiconductor integrated circuit blocks, each of said blocks being comprised of (a) at least a plurality of bipolar transistors, a plurality of resistors interconnected to form the principal circuit thereof; (b) a plurality of metal pads on said block being connected to and providing electrical access to various points, respectively, of said principal circuit; (c) a separate test circuit including: one bipolar transistor having been formed all together simultaneously with at least some of said plurality of transistors; and one resistor having been formed simultaneously with at least some of said plurality of resistors; and said one transistor and said one resistor of said test circuit being formed in only one electrically isolated pocket of said each semiconductor block.

Claim 10

An integrated circuit wafer consisting essentially of a matrix of crystalline semiconductor integrated circuit blocks, each of said blocks being comprised of (a) at least a plurality of bipolar transistors, a plurality of resistors interconnected to form the principal circuit thereof; (b) a plurality of metal pads on said block being connected to and providing electrical access to various points, respectively, of said principal circuit; (c) a separate test circuit including: one bipolar transistor having been formed all together simultaneously with at least some of said plurality of transistors; and one resistor having been formed simultaneously with at least some of said plurality of resistors; and said one transistor and said one resistor of said test circuit being formed in only one electrically isolated pocket of said each semiconductor block.