M&A for minimizing data transfer to main memory from a writeback cache during a cache miss

Claim 3

The apparatus as set forth in claim 1, wherein, s equals one hundred and twenty eight (128); w equals two (2); n1 equals thirty-two (32); n2 equals sixteen (16); m equals two (2); and n3 equals eight (8).

Claim 4

A computer system comprising: a main memory for storing data; a cache memory having s sets of cache lines for caching a subset of the data stored in the main memory, s being greater than one, each set having w cache line(s), w being greater than or equal to one, each cache line having a cache line size of n1 bytes, each cache line being also divided in to m cache line segments of n2 bytes, each cache line further having a single address tag for all m cache segments and m modify bits corresponding to the m cache line segments individually denoting whether the corresponding cache line segments have been modified, n1, n2 and m being non-zero integers with n1=m×n2, and n2 and m are both greater than one; a plurality of write buffers coupled to the cache memory for buffering at least one cache line of data being evicted out of the cache memory to make room in the cache memory for incoming replacement data responsive to cache misses; a bus coupled to the write buffers and the main memory for transferring the buffered data to the main memory in quantities of n3 bytes at a time, n2 being a greater than one integer multiple of n3; a bus controller coupled to the write buffers for controlling conditional partial write back of the buffered data for only those cache line segments whose corresponding modify bits denote the cache line segments having been modified.

Claim 5

A computer system comprising: a main memory for storing data; a cache memory having s sets of cache lines for caching a subset of the data stored in the main memory, s being greater than one, each set having w cache line(s), w being greater than or equal to one, each cache line having a cache line size of n1 bytes, each cache line being also divided in to m cache line segments of n2 bytes, each cache line further having a single address tag for all m cache segments and m modify bits corresponding to the m cache line segments individually denoting whether the corresponding cache line segments have been modified, n1, n2 and m being non-zero integers with n1=m×n2, and n2 and m are both greater than one; a plurality of write buffers coupled to the cache memory for buffering at least one cache line of data being evicted out of the cache memory to make room in the cache memory for incoming replacement data responsive to cache misses; a bus coupled to the write buffers and the main memory for transferring the buffered data to the main memory in quantities of n3 bytes at a time, n2 being a greater than one integer multiple of n3; a bus controller coupled to the write buffers for controlling conditional partial write back of the buffered data for only those cache line segments whose corresponding modify bits denote the cache line segments having been modified.

Claim 6

The computer system as set forth in claim 3, wherein, s equals one hundred and twenty eight (128); w equals two (2); n1 equals thirty-two (32); n2 equals sixteen (16); m equals two (2); and n3 equals eight (8).