Diagnostic mode for a cache

Claim 2

A cache having an address bus for receiving addresses from a processor requesting data, and a data bus for providing requested data to the processor, comprising: a TAG memory, coupled to the address bus, having a plurality of valid bits, a plurality of disable bits, and a plurality of TAG locations for storing a plurality of TAG addresses, each TAG location having a valid bit of the plurality of valid bits and a disable bit of the plurality of disable bits associated therewith; a data memory, coupled to the data bus, having a plurality of storage locations for storing data, wherein said stored data may be invalid and wherein said storage locations may be defective, each storage location corresponding to a TAG location of the plurality of TAG locations, a valid bit of the plurality of valid bits for indicating if data stored in the storage location is invalid, and a disable bit of the plurality of disable bits for indicating if the storage location is defective; TAG memory decoder means for selecting a first subset of TAG locations and disable bits which correspond thereto in response to a first portion of the address provided onto the address bus; register means. coupled to the data bus and the TAG memory decoder, for storing information received from said data bus and selecting the first subset of TAG locations; and control-bit port means, coupled to the disable bits and the data bus, for coupling the disable bits which correspond to the first subset of TAG locations to the data bus.

Claim 3

The cache of claim 1 further comprising: TAG port means, coupled to the TAG memory and the data bus, for coupling a selected TAG location of the first subset of TAG locations to the data bus.

Claim 4

The cache of claim 2, wherein the TAG memory means is further characterized as selecting the valid bits which correspond to the first subset of TAG locations, and the control-bit port means is further characterized as coupling the valid bits which correspond to the first subset of TAG locations to the data bus.

Claim 5

A cache having an address bus for receiving addresses from a processor requesting data, and a data bus for providing requested data to the processor, comprising: a TAG memory, coupled to the address bus, having a plurality of valid bits and a plurality of TAG locations for storing a plurality of TAG addresses, each TAG location having a valid bit of the plurality of valid bits associated therewith; a data memory, coupled to the data bus, having a plurality of storage locations for storing data, wherein said stored data may be invalid, each storage location corresponding to a TAG location of the plurality of TAG locations and a valid bit of the plurality of valid bits for indicating if data stored in the storage location is invalid; detection means, coupled to the address bus, for detecting if the cache is to enter a diagnostic mode; control means, coupled to the data bus and the detection means, for coupling a selected TAG location to the data bus in response to entering the diagnostic mode, wherein the control means comprises: TAG memory decoder means, coupled to the address bus, for selecting a first subset of TAG locations and valid bits which correspond thereto in response to a first portion of the address provided onto the address bus; register means, coupled to the data bus and the TAG memory decoder, for storing information which corresponds to the first portion of the address and providing said information which corresponds to the first portion of the address to the TAG memory decoder means, whereby the information stored in the register selects a second subset of TAG locations which correspond to the first subset of TAG locations; and TAG port means, coupled to the TAG memory, the detection means, and the data bus, for coupling a selected TAG location of the first subset of TAG locations.

Claim 6

A cache having an address bus for receiving addresses from a processor requesting data, and a data bus for providing requested data to the processor, comprising: a TAG memory, coupled to the address bus, having a plurality of valid bits and a plurality of TAG locations for storing a plurality of TAG addresses, each TAG location having a valid bit of the plurality of valid bits associated therewith; a data memory, coupled to the data bus, having a plurality of storage locations for storing data, wherein said stored data may be invalid, each storage location corresponding to a TAG location of the plurality of TAG locations and a valid bit of the plurality of valid bits for indicating if data stored in the storage location is invalid; detection means, coupled to the address bus, for detecting if the cache is to enter a diagnostic mode; control means, coupled to the data bus and the detection means, for coupling a selected TAG location to the data bus in response to entering the diagnostic mode, wherein the control means comprises: TAG memory decoder means, coupled to the address bus, for selecting a first subset of TAG locations and valid bits which correspond thereto in response to a first portion of the address provided onto the address bus; register means, coupled to the data bus and the TAG memory decoder, for storing information which corresponds to the first portion of the address and providing said information which corresponds to the first portion of the address to the TAG memory decoder means, whereby the information stored in the register selects a second subset of TAG locations which correspond to the first subset of TAG locations; and TAG port means, coupled to the TAG memory, the detection means, and the data bus, for coupling a selected TAG location of the first subset of TAG locations.

Claim 7

The cache of claim 4 wherein the detection means is further characterized as selecting the selected TAG location of the first subset of TAG locations.

Claim 8

A cache having an address bus for receiving addresses from a processor requesting data, and a data bus for providing requested data to the processor, comprising: a TAG memory, coupled to the address bus, having a plurality of control bits and a plurality of TAG locations for storing a plurality of TAG addresses, each TAG location having a set of control bits of the plurality of control bits associated therewith, said TAG locations being divided into a plurality of subsets; a data memory, coupled to the data bus, having a plurality of storage locations for storing data, each storage location corresponding to a TAG location of the plurality of TAG locations; TAG memory decoder means, coupled to the address bus, for selecting a particular subset of TAG locations and the sets of control bits which correspond thereto as determined by a first portion of the address provided onto the address bus; register means, coupled to the data bus and the TAG memory decoder means, for storing information received from the data bus which corresponds to the first portion of the address and providing said information which corresponds to the first portion of the address to the TAG memory decoder means, whereby the information stored in the register means selects a particular subset of TAG locations and the subsets of control bits which correspond thereto; detection means, coupled to the address bus, for detecting if the cache is to enter a diagnostic mode; control-bits port means, coupled to the TAG memory, the detection means, and the data bus, for coupling the subsets of control bits which correspond to the subset of TAG locations selected by the register means to the data bus in response to the detection means detecting that the cache is to enter the diagnostic mode.

Claim 9

A cache having an address bus for receiving addresses from a processor requesting data, and a data bus for providing requested data to the processor, comprising: a TAG memory, coupled to the address bus, having a plurality of control bits and a plurality of TAG locations for storing a plurality of TAG addresses, each TAG location having a set of control bits of the plurality of control bits associated therewith, said TAG locations being divided into a plurality of subsets; a data memory, coupled to the data bus, having a plurality of storage locations for storing data, each storage location corresponding to a TAG location of the plurality of TAG locations; TAG memory decoder means, coupled to the address bus, for selecting a particular subset of TAG locations and the sets of control bits which correspond thereto as determined by a first portion of the address provided onto the address bus; register means, coupled to the data bus and the TAG memory decoder means, for storing information received from the data bus which corresponds to the first portion of the address and providing said information which corresponds to the first portion of the address to the TAG memory decoder means, whereby the information stored in the register means selects a particular subset of TAG locations and the subsets of control bits which correspond thereto; detection means, coupled to the address bus, for detecting if the cache is to enter a diagnostic mode; control-bits port means, coupled to the TAG memory, the detection means, and the data bus, for coupling the subsets of control bits which correspond to the subset of TAG locations selected by the register means to the data bus in response to the detection means detecting that the cache is to enter the diagnostic mode.