US5455540A — Modified bang-bang phase detector with ternary ou…

Claim 1

Independent Claim 91 words

A method for controlling a dock generator comprising: generating a dock signal; receiving a data signal from an external circuit; generating a first signal when a transition edge of said clock signal occurs after a transition edge of said data signal; generating a second signal when said transition edge of said clock signal occurs before said transition edge of said data signal; and generating a third signal when said data signal remains in a same signal state for at least two transition edges of a same type of said dock signal.

Claim 2

Independent Claim 91 words

A method for controlling a dock generator comprising: generating a dock signal; receiving a data signal from an external circuit; generating a first signal when a transition edge of said clock signal occurs after a transition edge of said data signal; generating a second signal when said transition edge of said clock signal occurs before said transition edge of said data signal; and generating a third signal when said data signal remains in a same signal state for at least two transition edges of a same type of said dock signal.

Claim 3

Dependent Claim 38 words

The method of claim 1 further comprising: accelerating said dock signal in response to said first signal; delaying said dock signal in response to said second signal; and maintaining said dock signal in response to said third signal.

Claim 4

Dependent Claim 42 words

The method of claim 2 wherein accelerating said clock signal in response to said first signal comprises increasing frequency of said clock signal and wherein delaying said clock signal in response to said second signal comprises decreasing frequency of said dock signal.

Claim 5

Dependent Claim 46 words

The method of claim 2 wherein accelerating said dock signal in response to said first signal comprises shifting in a phase of said clock signal and wherein delaying said dock signal in response to said second signal comprises shifting out said phase of said clock signal.

Claim 6

Dependent Claim 51 words

The method of claim 1 further comprising: generating a first signal state when said transition edge of said data signal occurs; and generating a second signal state when said data signal remains in said same signal state for at least two transition edges of a same type of said clock signal.

Claim 7

Dependent Claim 52 words

The method of claim 1 further comprising: generating a first signal state when said transition edge of said data signal occurs before said transition edge of said clock signal; and generating a second signal state when said transition edge of said data signal occurs after said transition edge of said clock signal.

Claim 8

Dependent Claim 21 words

The method of claim 1 wherein said transition edges of a same type of said dock signal are rising transition edges.

Claim 9

Dependent Claim 21 words

The method of claim 1 wherein said transition edges of a same type of said dock signal are falling transition edges.

Claim 10

Dependent Claim 96 words

A phase detector for indicating phase comprising: a data input allowing said phase detector to receive a data signal from a data signal source; a dock input allowing said phase detector to receive a clock signal from a dock signal source; first circuitry coupled to said data input and said clock input operable to indicate a transition edge of said data signal; and second circuitry coupled to said data input and said dock input operable to indicate a position of said transition edge of said data signal relative to a transition edge of said dock signal.

Claim 11

Dependent Claim 96 words

A phase detector for indicating phase comprising: a data input allowing said phase detector to receive a data signal from a data signal source; a dock input allowing said phase detector to receive a clock signal from a dock signal source; first circuitry coupled to said data input and said clock input operable to indicate a transition edge of said data signal; and second circuitry coupled to said data input and said dock input operable to indicate a position of said transition edge of said data signal relative to a transition edge of said dock signal.

Claim 12

Dependent Claim 62 words

The phase detector of claim 9 wherein said first circuitry is operable to generate a first signal state when said phase detector receives said transition edge of said data signal and operable to generate a second signal state when said data signal remains in a same signal state for at least two transition edges of a same type of said dock signal.

Claim 13

Dependent Claim 60 words

The phase detector of claim 9 wherein said second circuitry is operable to generate a first signal state when said transition edge of said data signal occurs before said transition edge of said clock signal and operable to generate a second signal state when said transition edge of said data signal occurs after said transition edge of said clock signal.

Claim 14

Dependent Claim 106 words

The phase detector of claim 9 further comprising: third circuitry coupled to said first circuitry and said second circuitry operable to generate a first signal when said transition edge of said clock signal occurs after said transition edge of said data signal, wherein said third circuitry is operable to generate said second signal when said transition edge of said clock signal occurs before said transition edge of said data signal, and wherein said third circuitry is operable to generate said third signal when said data signal remains in a same signal state for at least two transition edges of a same type of said dock signal.

Claim 15

Dependent Claim 34 words

The phase detector of claim 12 wherein said first signal is a first voltage potential, wherein said second signal is a second voltage potential and wherein said third signal is a third voltage potential.

Claim 16

Dependent Claim 88 words

The phase detector of claim 11 further comprising: third circuitry coupled to said first circuitry and said second circuitry operable to generate a first signal when said first circuitry and said second circuitry generate a first signal state, wherein said third circuitry is operable to generate a second signal when said first circuitry generates said first signal state and said second circuitry generates a second signal state, and wherein said third circuitry is operable to generate a third signal when said first circuitry generates said second signal state.

Claim 17

Dependent Claim 32 words

The phase detector of claim 9 further comprising: a delay circuit coupled to said data input and said second circuitry operable to delay receipt of said data signal by said second circuitry.

Claim 18

Dependent Claim 26 words

The phase detector of claim 15 further comprising: a data output coupled to said delay circuit allowing said phase detector to output a delayed data signal.

Claim 19

Independent Claim 101 words

An apparatus for controlling a dock generator comprising: means for generating a clock signal; means for receiving a data signal from an external circuit; means for generating a first signal when a transition edge of said clock signal occurs after a transition edge of said data signal; means for generating a second signal when said transition edge of said dock signal occurs before said transition edge of said data signal; and means for generating a third signal when said data signal remains in a same signal state for at least two transition edges of a same type of said clock signal.

Claim 20

Independent Claim 101 words

An apparatus for controlling a dock generator comprising: means for generating a clock signal; means for receiving a data signal from an external circuit; means for generating a first signal when a transition edge of said clock signal occurs after a transition edge of said data signal; means for generating a second signal when said transition edge of said dock signal occurs before said transition edge of said data signal; and means for generating a third signal when said data signal remains in a same signal state for at least two transition edges of a same type of said clock signal.

Claim 21

Dependent Claim 42 words

The apparatus of claim 17 further comprising: means for indicating when said transition edge of said data signal occurs; and means for indicating a position of said transition edge of said data signal relative to said transition edge of said clock signal.

Claim 22

Dependent Claim 162 words

A phase-locked loop circuit comprising: a clock generator operable to accelerate a clock signal in response to a first signal, operable to delay said dock signal in response to a second signal, and operable to maintain said clock signal in response to a third signal; a phase detector coupled to said clock generator operable to generate said first signal when a transition edge of said dock signal occurs after a transition edge of a data signal, wherein said phase detector is operable to generate said second signal when said transition edge of said dock signal occurs before said transition edge of said data signal, and wherein said phase detector is operable to generate said third signal when said data signal remains in a same signal state for at least two transition edges of a same type of said clock signal; and a data input coupled to said phase detector allowing said phase detector to receive said data signal from an external circuit.

Claim 23

Dependent Claim 162 words

A phase-locked loop circuit comprising: a clock generator operable to accelerate a clock signal in response to a first signal, operable to delay said dock signal in response to a second signal, and operable to maintain said clock signal in response to a third signal; a phase detector coupled to said clock generator operable to generate said first signal when a transition edge of said dock signal occurs after a transition edge of a data signal, wherein said phase detector is operable to generate said second signal when said transition edge of said dock signal occurs before said transition edge of said data signal, and wherein said phase detector is operable to generate said third signal when said data signal remains in a same signal state for at least two transition edges of a same type of said clock signal; and a data input coupled to said phase detector allowing said phase detector to receive said data signal from an external circuit.

Claim 24

Dependent Claim 14 words

The circuit of claim 19 wherein said clock generator is a voltage controlled oscillator.

Claim 25

Dependent Claim 38 words

The circuit of claim 19 wherein said clock generator is operable to accelerate said dock signal by increasing frequency of said dock signal and is operable to delay said dock signal by decreasing frequency of said dock signal.

Claim 26

Dependent Claim 42 words

The circuit of claim 19 wherein said dock generator is operable to accelerate said clock signal by shifting in a phase of said dock signal and is operable to delay said clock signal by shifting out said phase of said dock signal.

Claim 27

Dependent Claim 33 words

The circuit of claim 19 wherein said first signal is a first voltage potential, wherein said second signal is a second voltage potential and wherein said third signal is a third voltage potential.

Claim 28

Dependent Claim 18 words

The circuit of claim 19 wherein said transition edge of said dock signal is a rising transition edge.

Claim 29

Dependent Claim 18 words

The circuit of claim 19 wherein said transition edge of said clock signal is a falling transition edge.

Claim 30

Dependent Claim 21 words

The circuit of claim 19 wherein said transition edges of a same type are rising transition edges of said clock signal.

Claim 31

Dependent Claim 21 words

The circuit of claim 19 wherein said transition edges of a same type are falling transition edges of said clock signal.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1998-10-02	1999-04-03	1999-10-03	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2002-10-02	2003-04-03	2003-10-03	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2006-10-02	2007-04-03	2007-10-03	$7700.00	Window Closed / Lapsed

Modified bang-bang phase detector with ternary output

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