Method for simultaneously fabricating bipolar and complementary field effect transistors

Claim 1

A method of fabricating a semiconductor structure comprising the steps of: depositing an epitaxial layer of semiconductor material over a semiconductor substrate; implanting first conductivity type impurity into a bipolar region of the epitaxial layer for forming a base of a bipolar transistor; thereafter implanting second conductivity type impurity into the bipolar region of the epitaxial layer for forming a collector contact and an emitter of the bipolar transistor and into an FET region of the epitaxial layer for forming source and drain regions of an FET transistor; masking a base contact region of the base of the bipolar transistor from the second conductivity type impurity implant; and thereafter oxidizing the epitaxial layer for forming a differential thickness oxide layer which is thicker over the source and drain regions, the collector contact and the emitter than over the base contact region.

Claim 2

A method of fabricating a semiconductor structure comprising the steps of: depositing an epitaxial layer of semiconductor material over a semiconductor substrate; implanting first conductivity type impurity into a bipolar region of the epitaxial layer for forming a base of a bipolar transistor; thereafter implanting second conductivity type impurity into the bipolar region of the epitaxial layer for forming a collector contact and an emitter of the bipolar transistor and into an FET region of the epitaxial layer for forming source and drain regions of an FET transistor; masking a base contact region of the base of the bipolar transistor from the second conductivity type impurity implant; and thereafter oxidizing the epitaxial layer for forming a differential thickness oxide layer which is thicker over the source and drain regions, the collector contact and the emitter than over the base contact region.

Claim 13

A method for fabricating a semiconductor structure comprising the steps of: depositing an epitaxial layer of semiconductor material over a semiconductor substrate; implanting first conductivity type impurity into a bipolar region of the epitaxial layer for forming a base of a bipolar transistor; defining a first gate electrode on a portion of the epitaxial layer defining a first FET region; defining a second gate electrode on a portion of the epitaxial layer defining a second FET region; implanting second conductivity type impurity into the second FET region of the epitaxial layer for forming source and drain regions of an FET transistor adjacent to the second gate electrode after implanting the first conductivity type impurity; implanting second conductivity type impurity into the bipolar region of the epitaxial layer for forming a collector contact and an emitter of a bipolar transistor after implanting the first conductivity type impurity; masking the first FET region and a base contact region of the base of the bipolar transistor from the second conductivity type impurity implants into the second FET region and bipolar region; and oxidizing the epitaxial layer for forming a differential thickness oxide layer which is thicker over the source and drain regions adjacent to the second gate electrode and the collector contact and emitter than over the base contact region and regions of the epitaxial layer adjacent to the first gate electrode.

Claim 14

A method for fabricating a semiconductor structure comprising the steps of: depositing an epitaxial layer of semiconductor material over a semiconductor substrate; implanting first conductivity type impurity into a bipolar region of the epitaxial layer for forming a base of a bipolar transistor; defining a first gate electrode on a portion of the epitaxial layer defining a first FET region; defining a second gate electrode on a portion of the epitaxial layer defining a second FET region; implanting second conductivity type impurity into the second FET region of the epitaxial layer for forming source and drain regions of an FET transistor adjacent to the second gate electrode after implanting the first conductivity type impurity; implanting second conductivity type impurity into the bipolar region of the epitaxial layer for forming a collector contact and an emitter of a bipolar transistor after implanting the first conductivity type impurity; masking the first FET region and a base contact region of the base of the bipolar transistor from the second conductivity type impurity implants into the second FET region and bipolar region; and oxidizing the epitaxial layer for forming a differential thickness oxide layer which is thicker over the source and drain regions adjacent to the second gate electrode and the collector contact and emitter than over the base contact region and regions of the epitaxial layer adjacent to the first gate electrode.

Claim 21

A method for fabricating a semiconductor structure comprising the steps of: depositing an epitaxial layer of semiconductor material over a semiconductor substrate; implanting P conductivity type impurity into a bipolar region of the epitaxial layer for forming a base of an NPN bipolar transistor; defining a PMOS gate electrode on a portion of the epitaxial layer defining a PMOS FET region; defining an NMOS gate electrode on a portion of the epitaxial layer defining an NMOS FET region; implanting N conductivity type impurity into the NMOS FET region of the epitaxial layer for forming source and drain regions of an NMOS FET transistor adjacent to the NMOS gate electrode after implanting the P conductivity type impurity; implanting N conductivity type impurity into the bipolar region of the epitaxial layer for forming a collector contact and an emitter of the NPN bipolar transistor after implanting the P conductivity type impurity; masking the PMOS FET region and a base contact region of the base of the NPN bipolar transistor from the N conductivity type impurity implants into the NMOS FET region and the bipolar region; and oxidizing the epitaxial layer for forming a differential thickness oxide layer which is thicker over the source and drain regions adjacent to the NMOS gate electrode and the collector contact and emitter than over the base contact region and regions of the epitaxial layer adjacent to the PMOS gate electrode.

Claim 22

A method for fabricating a semiconductor structure comprising the steps of: depositing an epitaxial layer of semiconductor material over a semiconductor substrate; implanting P conductivity type impurity into a bipolar region of the epitaxial layer for forming a base of an NPN bipolar transistor; defining a PMOS gate electrode on a portion of the epitaxial layer defining a PMOS FET region; defining an NMOS gate electrode on a portion of the epitaxial layer defining an NMOS FET region; implanting N conductivity type impurity into the NMOS FET region of the epitaxial layer for forming source and drain regions of an NMOS FET transistor adjacent to the NMOS gate electrode after implanting the P conductivity type impurity; implanting N conductivity type impurity into the bipolar region of the epitaxial layer for forming a collector contact and an emitter of the NPN bipolar transistor after implanting the P conductivity type impurity; masking the PMOS FET region and a base contact region of the base of the NPN bipolar transistor from the N conductivity type impurity implants into the NMOS FET region and the bipolar region; and oxidizing the epitaxial layer for forming a differential thickness oxide layer which is thicker over the source and drain regions adjacent to the NMOS gate electrode and the collector contact and emitter than over the base contact region and regions of the epitaxial layer adjacent to the PMOS gate electrode.

Claim 29

A method of fabricating a semiconductor structure comprising the steps of, in order: depositing an epitaxial layer of semiconductor material over a semiconductor structure; depositing an oxide-exclusion layer over the epitaxial layer, the oxide-exclusion layer being formed of a material which substantially prevents oxidation of the epitaxial layer; etching the oxide-exclusion layer for forming openings overlying portions of the epitaxial layer where a field oxide layer is to be formed; implanting an impurity into the epitaxial layer using the oxide-exclusion layer as a mask; oxidizing the exposed portions of the epitaxial layer for forming the field oxide layer; removing the oxide exclusion layer; implanting first conductivity type impurity into a bipolar region of the epitaxial layer for forming a base of a bipolar transistor; blanket implanting first conductivity type impurity into the epitaxial layer without a mask for adjusting a voltage threshold of the semiconductor structure; implanting second conductivity type impurity into the bipolar region of the epitaxial layer for forming a collector contact and an emitter of the bipolar transistor and into an FET region of the substrate for forming source and drain regions of an FET transistor; masking a base contact region of the base of the bipolar transistor from the second conductivity type impurity implants; oxidizing the epitaxial layer for forming a differential thickness oxide layer which is thicker over the source and drain regions, the collector contact and the emitter than over the base contact region; and blanket implanting first conductivity type impurity into the epitaxial layer, the energy of the implant being such that the first conductivity type impurity penetrates only the portions of the oxide layer not covering the source and drain regions, the collector contact and the emitter.

Claim 30

A method of fabricating a semiconductor structure comprising the steps of, in order: depositing an epitaxial layer of semiconductor material over a semiconductor structure; depositing an oxide-exclusion layer over the epitaxial layer, the oxide-exclusion layer being formed of a material which substantially prevents oxidation of the epitaxial layer; etching the oxide-exclusion layer for forming openings overlying portions of the epitaxial layer where a field oxide layer is to be formed; implanting an impurity into the epitaxial layer using the oxide-exclusion layer as a mask; oxidizing the exposed portions of the epitaxial layer for forming the field oxide layer; removing the oxide exclusion layer; implanting first conductivity type impurity into a bipolar region of the epitaxial layer for forming a base of a bipolar transistor; blanket implanting first conductivity type impurity into the epitaxial layer without a mask for adjusting a voltage threshold of the semiconductor structure; implanting second conductivity type impurity into the bipolar region of the epitaxial layer for forming a collector contact and an emitter of the bipolar transistor and into an FET region of the substrate for forming source and drain regions of an FET transistor; masking a base contact region of the base of the bipolar transistor from the second conductivity type impurity implants; oxidizing the epitaxial layer for forming a differential thickness oxide layer which is thicker over the source and drain regions, the collector contact and the emitter than over the base contact region; and blanket implanting first conductivity type impurity into the epitaxial layer, the energy of the implant being such that the first conductivity type impurity penetrates only the portions of the oxide layer not covering the source and drain regions, the collector contact and the emitter.

Claim 33

A method for fabricating a semiconductor structure comprising the steps of, in order: depositing an epitaxial layer of semiconductor material over a semiconductor substrate; depositing an oxide-exclusion layer over the epitaxial layer, the oxide-exclusion layer being formed of a material which substantially prevents oxidation of the epitaxial layer; etching the oxide-exclusion layer for forming openings overlying portions of the epitaxial layer where a field oxide layer is to be formed; implanting a P conductivity type impurity into the epitaxial layer using the oxide-exclusion layer as a mask; oxidizing the exposed portions of the epitaxial layer for forming the field oxide layer; removing the oxide exclusion layer; implanting P conductivity type impurity into a bipolar region of the epitaxial layer for forming a base of an NPN bipolar transistor; blanket implanting P conductivity type impurity into the epitaxial layer without a mask for adjusting a voltage threshold of the semiconductor structure; oxidizing the epitaxial layer for forming a gate insulator layer overlying a PMOS FET region of the epitaxial layer and an NMOS FET region of the epitaxial layer; depositing a silicon layer over the gate insulator layer; and etching the gate insulator layer and the polysilicon layer for simultaneously forming a PMOS gate electrode in the PMOS FET region and an NMOS gate electrode in the NMOS FET region; implanting N conductivity type impurity into the epitaxial layer for forming source and drain regions of an NMOS FET transistor adjacent to the NMOS gate electrode and for forming a collector contact and an emitter of the NPN bipolar transistor; masking the PMOS FET region and a base contact region of the base of the NPN bipolar transistor from the N conductivity type implant; oxidizing the epitaxial layer for forming a differential thickness oxide layer which is thicker over the source and drain regions of the NMOS transistor and the collector contact and emitter of the NPN transistor than over the source and drain regions of the PMOS transistor and the base contact region of the NPN transistor; and blanket implanting P conductivity type impurity into the epitaxial layer, the energy of the implant being such that the P conductivity type impurity penetrates only thinner portions of the oxide layer for forming a source and drain of a PMOS FET transistor adjacent to the PMOS gate electrode.

Claim 34

A method for fabricating a semiconductor structure comprising the steps of, in order: depositing an epitaxial layer of semiconductor material over a semiconductor substrate; depositing an oxide-exclusion layer over the epitaxial layer, the oxide-exclusion layer being formed of a material which substantially prevents oxidation of the epitaxial layer; etching the oxide-exclusion layer for forming openings overlying portions of the epitaxial layer where a field oxide layer is to be formed; implanting a P conductivity type impurity into the epitaxial layer using the oxide-exclusion layer as a mask; oxidizing the exposed portions of the epitaxial layer for forming the field oxide layer; removing the oxide exclusion layer; implanting P conductivity type impurity into a bipolar region of the epitaxial layer for forming a base of an NPN bipolar transistor; blanket implanting P conductivity type impurity into the epitaxial layer without a mask for adjusting a voltage threshold of the semiconductor structure; oxidizing the epitaxial layer for forming a gate insulator layer overlying a PMOS FET region of the epitaxial layer and an NMOS FET region of the epitaxial layer; depositing a silicon layer over the gate insulator layer; and etching the gate insulator layer and the polysilicon layer for simultaneously forming a PMOS gate electrode in the PMOS FET region and an NMOS gate electrode in the NMOS FET region; implanting N conductivity type impurity into the epitaxial layer for forming source and drain regions of an NMOS FET transistor adjacent to the NMOS gate electrode and for forming a collector contact and an emitter of the NPN bipolar transistor; masking the PMOS FET region and a base contact region of the base of the NPN bipolar transistor from the N conductivity type implant; oxidizing the epitaxial layer for forming a differential thickness oxide layer which is thicker over the source and drain regions of the NMOS transistor and the collector contact and emitter of the NPN transistor than over the source and drain regions of the PMOS transistor and the base contact region of the NPN transistor; and blanket implanting P conductivity type impurity into the epitaxial layer, the energy of the implant being such that the P conductivity type impurity penetrates only thinner portions of the oxide layer for forming a source and drain of a PMOS FET transistor adjacent to the PMOS gate electrode.