Method of making substrate injection logic operator structure

Claim 1

A process for manufacturing a substrate-fed logic operator, including a PNP injection transistor and an NPN multicollector transistor on a semiconductor wafer, comprising the steps of: (a) providing a low-doped P-type substrate, (b) boron implanting the substrate through a first masking layer to form a first P-type layer with high doping concentration, (c) phosphorus implanting the substrate through a second masking layer covering part of the first P-type layer to form a second N-type layer having a high doping level, and annealing the wafer, (d) forming, by epitaxy, a third N-type layer having a low doping level and overlying all previous layers, (e) phosphorus diffusing the epitaxial third layer through a third masking layer to subsequently form an emitter access to the second N-type layer through said epitaxial third layer, and annealing, (f) boron diffusing the third epitaxial layer through a fourth masking layer, to form a fourth P-type layer of high doping level, corresponding to base contacts and separation between collectors of said NPN multicollector transistor, said fourth layer subsequently diffusing down to said second layer, (g) boron implanting said third epitaxial layer through a fifth masking layer to form a fifth P-type layer of intermediate doping level, corresponding to the base of said NPN multicollector transistor, (h) introducing an N-type impurity in the epitaxial third layer through a sixth masking layer to form a sixth N-type layer of high doping level corresponding to collector regions of said NPN multicollector transistor, and (i) forming metal contacts with said emitter access, with said fourth layer and with said sixth layer.